Gate cut in RMG

Patent metadata

Field	Value
Publication number	US-10692990-B2
Application number	US-201916599229-A
Country	US
Kind code	B2
Filing date	Oct 11, 2019
Priority date	May 29, 2018
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.

First claim

What is claimed is:

1. A method for performing a gate cut in a field effect transistor (FET) structure, the method comprising:
forming a plurality of fins and at least one insulating pillar over a semiconductor substrate;
depositing a first work function metal layer;
removing the first work function metal layer from a first set of fins;
depositing a second work function metal layer;
depositing an organic patterning layer over the second work function metal layer;
forming at least one gate trench through the organic patterning layer;
filling the at least one gate trench with an insulating material;
forming a conductive adhesion liner over the insulating material and the second work function metal layer; and
depositing a conductive material over the conductive adhesion liner.

2. The method of claim 1 , further comprising forming a dielectric layer over the plurality of fins and over the at least one insulating pillar before depositing the first work function metal layer.

3. The method of claim 2 , further comprising depositing a patterning stack over the organic patterning layer and before forming the at least one gate trench.

4. The method of claim 1 , further comprising employing work function metal patterning to remove the first work function metal layer prior to forming the at least one gate trench.

5. The method of claim 1 , wherein the conductive material is tungsten (W) and the insulating material is a nitride-based insulator.

6. The method of claim 1 , wherein the at least one insulating pillar is a silicon nitride (SiN) gate cut fill pillar.

7. The method of claim 1 , wherein the conductive adhesion liner is a titanium nitride (TiN) adhesion liner.

8. The method of claim 1 , further comprising recessing the conductive material to expose a top surface of the insulating material and the top surface of the at least one insulating pillar.

9. A method for performing a gate cut in a field effect transistor (FET) structure, the method comprising:
forming a plurality of fins and at least one insulating pillar over a semiconductor substrate;
depositing a first work function metal layer;
removing the first work function metal layer from a first set of fins;
depositing a second work function metal layer;
depositing an organic patterning layer over the second work function metal layer;
forming at least one gate trench through the organic patterning layer; and
filling the at least one gate trench with an insulating material.

10. The method of claim 9 , further comprising forming a conductive adhesion liner over the insulating material and the second work function metal layer.

11. The method of claim 10 , further comprising depositing a conductive material over the conductive adhesion liner.

12. The method of claim 11 , further comprising forming a dielectric layer over the plurality of fins and over the at least one insulating pillar before depositing the first work function metal layer.

13. The method of claim 12 , further comprising depositing a patterning stack over the organic patterning layer and before forming the at least one gate trench.

14. The method of claim 13 , further comprising employing work function metal patterning to remove the first work function metal layer prior to forming the at least one gate trench.

15. The method of claim 14 , wherein the conductive material is tungsten (W) and the insulating material is a nitride-based insulator.

16. The method of claim 15 , wherein the at least one insulating pillar is a silicon nitride (SiN) gate cut fill pillar.

17. The method of claim 16 , wherein the conductive adhesion liner is a titanium nitride (TiN) adhesion liner.

18. The method of claim 17 , further comprising recessing the conductive material to expose a top surface of the insulating material and the top surface of the at least one insulating pillar.

Assignees

• IBM

Inventors

• Bao Ruqiang
• Kanakasabapathy Siva
• Greene Andrew M

Classifications

• H10P76/2043

  using an anti-reflective coating · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title

• H10W20/033

  in openings in dielectrics · CPC title