Integrated circuit device

Patent metadata

Field	Value
Publication number	US-11710739-B2
Application number	US-202117372896-A
Country	US
Kind code	B2
Filing date	Jul 12, 2021
Priority date	Dec 2, 2020
Publication date	Jul 25, 2023
Grant date	Jul 25, 2023

Abstract

An integrated circuit device including a substrate including first and second device regions; a first fin active region on the first device region; a second fin active region on the second device region; an isolation film covering side walls of the active regions; gate cut insulating patterns on the isolation film on the device regions; a gate line extending on the fin active regions, the gate line having a length limited by the gate cut insulating patterns; and an inter-region insulating pattern on the isolation film between the fin active regions and at least partially penetrating the gate line in a vertical direction, wherein the inter-region insulating pattern has a bottom surface proximate to the substrate, a top surface distal to the substrate, and a side wall linearly extending from the bottom to the top surface.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
a substrate including a first device region and a second device region;
a first fin active region extending in a first horizontal direction on the first device region;
a second fin active region extending in the first horizontal direction on the second device region;
an isolation film covering opposite side walls of each of the first fin active region and the second fin active region;
a plurality of gate cut insulating patterns on the isolation film on the first device region and the second device region;
a gate line extending on the first fin active region and the second fin active region in a second horizontal direction that crosses the first horizontal direction, the gate line having a length in the second horizontal direction limited by the plurality of gate cut insulating patterns; and
an inter-region insulating pattern on the isolation film between the first fin active region and the second fin active region and at least partially penetrating the gate line in a vertical direction,
wherein the inter-region insulating pattern has a bottommost surface proximate to the substrate, a topmost surface distal to the substrate, and a flat side wall linearly extending an entire distance from the bottommost surface to the topmost surface.

2. The integrated circuit device as claimed in claim 1 , wherein a height of the inter-region insulating pattern in the vertical direction is less than a height of each of the plurality of gate cut insulating patterns in the vertical direction.

3. The integrated circuit device as claimed in claim 1 , further comprising:
at least one first nanosheet on the first fin active region and surrounded by the gate line; and
at least one second nanosheet on the second fin active region and surrounded by the gate line,
wherein a level of the top surface of the inter-region insulating pattern is lower than a level of a topmost surface of each of the at least one first nanosheet and the at least one second nanosheet.

4. The integrated circuit device as claimed in claim 1 , wherein a first shortest distance in the second horizontal direction between the inter-region insulating pattern and the first fin active region is different from a second shortest distance in the second horizontal direction between the inter-region insulating pattern and the second fin active region.

5. The integrated circuit device as claimed in claim 1 , further comprising:
at least one first nanosheet on the first fin active region and surrounded by the gate line; and
at least one second nanosheet on the second fin active region and surrounded by the gate line,
wherein the at least one first nanosheet or the at least one second nanosheet is at a higher level than the top surface of the inter-region insulating pattern.

6. The integrated circuit device as claimed in claim 1 , wherein the top surface of the inter-region insulating pattern is a non-planar surface.

7. The integrated circuit device as claimed in claim 1 , wherein:
the gate line includes:
a first portion covering the first fin active region on the first device region and having a first stack structure,
a second portion covering the second fin active region on the second device region and having a second stack structure that is different from the first stack structure, and
a gate connecting portion integrally connected to the first portion and the second portion and covering the top surface of the inter-region insulating pattern, and
the gate connecting portion has a structure different from the first stack structure and the second stack structure.

8. The integrated circuit device as claimed in claim 1 , wherein:
the gate line includes a first gate portion on the first device region and a second gate portion on the second device region, and
the first gate portion is separated from the second gate portion with the inter-region insulating pattern between the first gate portion and the second gate portion in the second horizontal direction.

9. The integrated circuit device as claimed in claim 8 , further comprising:
a first gate contact on the gate line and connected to the first gate portion of the gate line;
a second gate contact on the gate line and connected to the second gate portion of the gate line; and
a conductive line on the first gate contact and the second gate contact and connected to the first gate contact and the second gate contact.

10. An integrated circuit device, comprising:
a substrate including a first device region and a second device region separated from the first device region;
a first fin active region extending in a first horizontal direction on the first device region;
a second fin active region extending in the first horizontal direction on the second device region;
an isolation film covering opposite side walls of each of the first fin active region and the second fin active region;
a gate line extending on the first device region and the second device region in a second horizontal direction that crosses the first horizontal direction;
a first nanosheet stack facing a first fin top of the first fin active region at a position separated from the first fin top in a vertical direction, the first nanosheet stack including at least one first nanosheet surrounded by the gate line;
a second nanosheet stack facing a second fin top of the second fin active region at a position separated from the second fin top in the vertical direction, the second nanosheet stack including at least one second nanosheet surrounded by the gate line; and
an inter-region insulating pattern on the isolation film between the first fin active region and the second fin active region and partially penetrating the gate line in the vertical direction,
wherein the inter-region insulating pattern has a bottommost surface contacting the isolation film, a topmost surface contacting the gate line, and a flat side wall linearly extending an entire distance from the bottommost surface to the topmost surface.

11. The integrated circuit device as claimed in claim 10 , wherein:
the gate line includes a gate connecting portion contacting the top surface of the inter-region insulating pattern, and
a length of the gate connecting portion in the vertical direction is less than a length of the inter-region insulating pattern in the vertical direction.

12. The integrated circuit device as claimed in claim 10 , wherein:
the gate line includes a gate connecting portion contacting the top surface of the inter-region insulating pattern, and
a length of the gate connecting portion in the vertical direction is greater than a length of the inter-region insulating pattern in the vertical direction.

13. The integrated circuit device as claimed in claim 10 , wherein:
the top surface of the inter-region insulating pattern is a non-planar surface, and
the gate line includes a gate connecting portion having a non-planar surface contacting the top surface of the inter-region insulating pattern.

14. The integrated circuit device as claimed in claim 10 , wherein a level of the top surface of the inter-region insulating pattern is lower than a level of a topmost surface of each of the first nanosheet stack and the second nanosheet stack.

15. The integrated circuit device as claimed in claim 10 , wherein a first shortest distance in the second horizontal direction between the inter-region insulating pattern and the first fin active region is less than a second shortest distance in the second horizontal direction between the inter-region insulating pattern and the second fin active region.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yang Junggil
• Kim Minju
• Koh Donghyi

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title