Replacement metal gate patterning for nanosheet devices

Patent metadata

Field	Value
Publication number	US-10410933-B2
Application number	US-201715602225-A
Country	US
Kind code	B2
Filing date	May 23, 2017
Priority date	May 23, 2017
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

This disclosure relates to a method of replacement metal gate patterning for nanosheet devices including: forming a first and a second nanosheet stack on a substrate, the first and the second nanosheet stacks being adjacent to each other and each including vertically adjacent nanosheets separated by a distance; depositing a first metal surrounding the first nanosheet stack and a second portion of the first metal surrounding the second nanosheet stack; forming an isolation region between the first nanosheet stack and the second nanosheet stack; removing the second portion of the first metal surrounding the second nanosheet stack with an etching process, the isolation region preventing the etching process from reaching the first portion of the first metal and thereby preventing removal of the first portion of the first metal; and depositing a second metal surrounding each of the nanosheets of the second nanosheet stack.

First claim

What is claimed is:

1. A method comprising:
forming a first and a second nanosheet stack on a substrate, the first and the second nanosheet stacks being adjacent to each other and each including vertically adjacent nanosheets separated by a distance;
depositing a first metal such that a first portion of the first metal surrounds each of the nanosheets of the first nanosheet stack and a second portion of the first metal surrounds each of the nanosheets of the second nanosheet stack;
forming a nitride isolation region between the first nanosheet stack and the second nanosheet stack, the nitride isolation region extending from a surface of the substrate to a top of the first nanosheet stack and a top of the second nanosheet stack;
removing the second portion of the first metal surrounding the second nanosheet stack with an etching process, the nitride isolation region preventing the etching process from reaching the first portion of the first metal and thereby preventing removal of the first portion of the first metal;
removing the nitride isolation region; and
depositing a second metal surrounding each of the nanosheets of the second nanosheet stack.

2. The method of claim 1 , further comprising forming a layer having a high dielectric constant (high-k) on the substrate and the nanosheets of the first and second nanosheet stacks before the depositing of the first metal.

3. The method of claim 2 , wherein the forming of the nitride isolation region includes:
before depositing the first metal, forming the nitride isolation region such that the first portion of the first metal is only connected to the second portion of the first metal by a layer of the first metal formed around the nitride isolation region.

4. The method of claim 3 , further comprising:
before removing the second portion of the first metal, covering the first portion of the first metal and a portion of the first metal around the nitride isolation region with a soft mask,
wherein the etching process removes only a fraction of the portion of the first metal between the soft mask and the nitride isolation region.

5. The method of claim 4 , further comprising:
prior to the forming of the nitride isolation region, forming a dummy gate that extends from the first nanosheet stack to the second nanosheet stack; and
removing a portion of the dummy gate at a first location between the first nanosheet stack and the second nanosheet stack.

6. The method of claim 5 , wherein the forming of the nitride isolation region includes forming the nitride isolation region between the first nanosheet stack and the second nanosheet stack at the first location where the portion of the dummy gate was removed.

7. The method of claim 2 , wherein during the depositing of the first metal, a third portion of the first metal is deposited on the high-k layer, the third portion of the first metal connecting the first and the second portions of the first metal.

8. The method of claim 7 , further comprising:
disconnecting the first portion and the second portion of the first metal by etching through the third portion of the first metal to expose a layer underlying the first metal, and
forming the nitride isolation region to cover a cross-section of the third portion of the first metal connected to the first portion of the first metal.

9. The method of claim 8 , wherein disconnecting the first portion and the second portion of the first metal includes:
covering the first and second portions of the first metal with a soft mask;
creating an opening in the soft mask to expose the third portion of the first metal; and
removing the exposed third portion of the first metal to expose the substrate.

10. The method of claim 9 , wherein the forming of the nitride isolation region includes filling the opening, directly on top of the substrate, with a dielectric material.

11. The method of claim 8 , wherein the disconnecting of the first portion and the second portion of the first metal by etching through the third portion of the first metal exposes the high-k layer.

12. The method of claim 11 , wherein the forming of the nitride isolation region includes:
covering the first portion of the first metal and a portion of the third portion of the first metal with a soft mask;
removing at least a portion of the third portion of the first metal next to the soft mask but not covered by the soft mask to expose the high-k layer; and
forming a dielectric material layer on the exposed high-k layer to a height above an exposed cross-section of the third portion of the first metal underneath the soft mask.

13. The method of claim 12 , wherein the forming of the nitride isolation region includes forming the dielectric material layer conformally over the exposed high-k layer, the second nanosheet stack, and the soft mask covering the first portion of the first metal.

14. The method of claim 1 , wherein the first metal includes a different material than the second metal.

15. The method of claim 1 , wherein the first nanosheet stack is a PFET device, and the second nanosheet stack is a NFET device.

16. The method of claim 1 , wherein the first metal is a PFET work function metal, and the second metal is a NFET work function metal.

17. The method of claim 1 , wherein the removing of the second portion of the first metal includes removing the first metal from between the nanosheets of the second nanosheet stack with an isotropic etch.

18. The method of claim 1 , wherein the nitride isolation region includes silicon nitride (SiN).

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Park Chanro
• Sung Min Gyu
• Kim Hoon
• Zang Hui
• Xu Guowei

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D64/013 Primary

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title