Three-dimensional memory device and method of making thereof using sacrificial material regrowth

Patent metadata

Field	Value
Publication number	US-12426267-B2
Application number	US-202217821677-A
Country	US
Kind code	B2
Filing date	Aug 23, 2022
Priority date	Aug 23, 2022
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A first-tier alternating stack of first-tier insulating layers and first-tier sacrificial material layers is formed over a substrate. A first-tier memory opening is formed, and is filled with a first-tier sacrificial memory opening fill structure. A second-tier alternating stack of second-tier insulating layers and second-tier sacrificial material layers is formed. An etch mask layer is formed, and a second-tier memory opening is formed through the second-tier alternating stack. An etch mask removal process is performed which collaterally removes a top portion of the first-tier sacrificial memory opening fill structure. A sacrificial pillar structure is formed by performing a selective material deposition process. An inter-tier memory opening is formed by removing the first-tier sacrificial memory opening fill structure and at least a central portion of the sacrificial pillar structure. A memory opening fill structure is formed, and the sacrificial material layers are replaced with electrically conductive layers.

First claim

What is claimed is:

1. A method of forming a memory device, comprising:
forming a first-tier structure including a first-tier alternating stack of first-tier insulating layers and first-tier sacrificial material layers over a substrate;
forming a first-tier memory opening through the first-tier alternating stack;
forming a first-tier sacrificial memory opening fill structure in the first-tier memory opening;
forming a second-tier structure including a second-tier alternating stack of second-tier insulating layers and second-tier sacrificial material layers over the first-tier structure;
forming an etch mask layer comprising an opening therethrough over the second-tier alternating stack;
forming a second-tier memory opening through the second-tier alternating stack, wherein a top surface of the first-tier sacrificial memory opening fill structure is physically exposed underneath the second-tier memory opening;
removing the etch mask layer employing an etch mask removal process that collaterally removes a top portion of the first-tier sacrificial memory opening fill structure;
forming a sacrificial pillar structure by performing a selective material deposition process that grows a sacrificial fill material from a top surface of a remaining portion of the first-tier sacrificial memory opening fill structure while suppressing growth of the sacrificial fill material from physically exposed surfaces of the first-tier alternating stack and the second-tier alternating stack;
forming an inter-tier memory opening by removing the first-tier sacrificial memory opening fill structure and at least a central portion of the sacrificial pillar structure;
forming a memory opening fill structure in the inter-tier memory opening, wherein the memory opening fill structure comprises a vertical stack of memory elements that are formed at levels of the first-tier sacrificial material layers and the second-tier sacrificial material layers; and
replacing the first-tier sacrificial material layers and the second-tier sacrificial material layers with electrically conductive layers.

2. The method of claim 1 , wherein:
the first-tier sacrificial memory opening fill structure comprises a first carbon-based material;
the etch mask layer comprises a second carbon-based material; and
the sacrificial pillar structure comprises a third carbon-based material.

3. The method of claim 2 , wherein:
the first carbon-based material comprises carbon atoms at an atomic concentration greater than 90%;
the second carbon-based material comprises carbon atoms at an atomic concentration greater than 90%; and
the third carbon-based material comprises carbon atoms at an atomic concentration greater than 90%.

4. The method of claim 3 , wherein:
the first, second and third carbon-based material comprises amorphous carbon;
the first-tier insulating layers and the second-tier insulating layers comprise silicon oxide layers; and
the first-tier sacrificial material layers and the second-tier sacrificial material layer comprise silicon nitride layers.

5. The method of claim 4 , wherein the first-tier sacrificial memory opening fill structure and the sacrificial pillar structure are removed by ashing.

6. The method of claim 1 , wherein:
the remaining portion of the first-tier sacrificial memory opening fill structure has a top surface located underneath a horizontal plane including a bottom surface of a topmost first-tier sacrificial material layer of the first-tier sacrificial material layers; and
a top surface of the sacrificial pillar structure is formed above a horizontal plane including a top surface of a topmost first-tier sacrificial material layer of the first-tier sacrificial material layers, and underneath a horizontal plane including a topmost surface of the first-tier structure.

7. The method of claim 1 , further comprising:
forming a sacrificial liner on a sidewall of the first-tier memory opening, wherein the first-tier sacrificial memory opening fill structure is formed on the sacrificial liner; and
removing the sacrificial liner after the removing the first-tier sacrificial memory opening fill structure.

8. The method of claim 1 , further comprising laterally expanding the second-tier memory opening and a top portion of the first-tier memory opening that overlies a top surface of the sacrificial pillar structure.

9. The method of claim 8 , wherein:
the second-tier memory opening and the top portion of the first-tier memory opening are laterally expanded such that a lateral dimension of a bottom portion of the second-tier memory opening has a greater lateral dimension than a lateral dimension of a bottom portion of the first-tier memory opening, and a lateral dimension of a top-portion of the second-tier memory opening has a greater lateral dimension than a lateral dimension of the first-tier memory opening at a height of a top surface of a topmost first-tier sacrificial material layer of the first-tier sacrificial material layers; and
the second-tier memory opening and the top portion of the first-tier memory opening are laterally expanded by performing:
a first isotropic etch process that laterally recesses physically exposed sidewalls of the second-tier insulating layers and a topmost first-tier insulating layer within the first-tier alternating stack by a first lateral recess distance; and
a second isotropic etch process that laterally recesses physically exposed sidewalls of the second-tier sacrificial material layers by a second lateral recess distance.

10. The method of claim 1 , further comprising:
forming a second-tier sacrificial memory opening fill structure in the second-tier memory opening and on the sacrificial pillar structure;
forming a third-tier alternating stack of third-tier insulating layers and third-tier sacrificial material layers over the second-tier alternating stack;
forming an additional etch mask layer over the third-tier alternating stack;
forming a third-tier memory opening through the third-tier alternating stack, wherein a top surface of the second-tier sacrificial memory opening fill structure is physically exposed underneath the third-tier memory opening;
removing the additional etch mask layer employing an additional etch mask removal process that collaterally removes a top portion of the second-tier sacrificial memory opening fill structure;
forming an additional sacrificial pillar structure by performing an additional selective material deposition process that grows an additional sacrificial fill material from a top surface of a remaining portion of the second-tier sacrificial memory opening fill structure while suppressing growth of the additional sacrificial fill material from physically exposed surfaces of the second-tier alternating stack and the third-tier alternating stack,
wherein the inter-tier memory opening is formed by removing the second-tier sacrificial memory opening fill structure and at least a central portion of the additional sacrificial pillar structure.

11. The method of claim 10 , further comprising forming at least one oxide layer and at least one nitride layer over the second-tier alternating stack followed by forming the third-tier alternating stack, wherein the at least one oxide layer has a higher wet etch rate than the third-tier insulating layers, and the at least one nitride layer has a higher wet etch rate than the third-tier sacrificial material layers.

12. The method of claim 10 , further comprising laterally expanding the third-tier memory opening and a top portion of the second-tier memory opening that overlies a top surface of the additional sacrificial pillar structure, wherein the additional sacrifici

Assignees

• Sandisk Technologies Llc
• Sandisk Technologies Inc

Inventors

• Zhou Bing
• Kanakamedala Senaka
• Makala Raghuveer S

Classifications

• H10P50/613

  of Group IV materials · CPC title

• H10P14/432

  using selective deposition · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title