Three-dimensional memory devices containing inter-tier dummy memory cells and methods of making the same

Patent metadata

Field	Value
Publication number	US-10056399-B2
Application number	US-201715445579-A
Country	US
Kind code	B2
Filing date	Feb 28, 2017
Priority date	Dec 22, 2016
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first memory opening fill structure extending through the first alternating stack and including a first memory film and a first vertical semiconductor channel, a joint-level electrically conductive layer overlying the first alternating stack, at least one joint-level doped semiconductor portion contacting a top surface of the first vertical semiconductor channel and located within, and electrically isolated from, the joint-level electrically conductive layer, a second alternating stack of second insulating layers and second electrically conductive layers located over the joint-level electrically conductive layer, and a second memory opening fill structure extending through the second alternating stack and including a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and vertically extends into the at least one joint-level doped semiconductor portion.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate;
a first memory opening fill structure extending through the first alternating stack and comprising a first memory film and a first vertical semiconductor channel that is laterally surrounded by the first memory film;
a joint-level electrically conductive layer overlying the first alternating stack;
at least one joint-level doped semiconductor portion contacting a top surface of the first vertical semiconductor channel and located within, and electrically isolated from, the joint-level electrically conductive layer;
a second alternating stack of second insulating layers and second electrically conductive layers located over the joint-level electrically conductive layer;
a second memory opening fill structure extending through the second alternating stack and comprising a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and vertically extends into the at least one joint-level doped semiconductor portion, wherein the first memory film and the second memory film are vertically spaced from each other by the at least one joint-level doped semiconductor portion;
a first annular dielectric spacer having a first material composition, contacting a top surface of the first memory film, and laterally surrounding the at least one joint-level doped semiconductor portion; and
a second annular dielectric spacer having a second material composition, contacting at least one of a top surface and an outer sidewall of the first annular dielectric spacer and a bottom surface of the second alternating stack, and laterally surrounding the at least one joint-level doped semiconductor portion, wherein the second material composition is different from the first material composition.

2. The three-dimensional memory device of claim 1 , wherein the first annular dielectric spacer is located at a same level as, and laterally surrounded by, the joint-level electrically conductive layer.

3. The three-dimensional memory device of claim 2 , further comprising:
a joint-level insulating layer overlying the joint-level electrically conductive layer;
an additional joint-level electrically conductive layer overlying the joint-level insulating layer and underlying the second alternating stack,
wherein the joint-level insulating layer and the additional joint-level electrically conductive layer are laterally spaced from the at the one joint-level doped semiconductor portion at least by a respective one of the first and second annular dielectric spacers.

4. The three-dimensional memory device of claim 3 , wherein
the at least one joint-level doped semiconductor portion comprises a first joint-level doped semiconductor portion and a second joint-level doped semiconductor portion.

5. The three-dimensional memory device of claim 3 , wherein:
the at least one joint-level doped semiconductor portion comprises a first joint-level doped semiconductor portion; a second joint-level doped semiconductor portion, and a third joint-level doped semiconductor portion;
the first annular dielectric spacer and the first joint-level doped semiconductor portion are located at a level of the joint-level electrically conductive layer;
the second annular dielectric spacer and the second joint-level doped semiconductor portion are located at a level of the joint-level insulator layer; and
a third annular dielectric spacer and the third joint-level doped semiconductor portion are located at a level of the additional joint-level electrically conductive layer.

6. The three-dimensional memory device of claim 2 , wherein:
a bottommost surface of the at least one joint-level doped semiconductor portion contacts a top surface of the first vertical semiconductor channel;
a topmost surface of the at least one joint-level doped semiconductor portion contacts a bottom surface of the second memory film;
a recessed surface of the at least one joint-level doped semiconductor portion contacts a bottommost surface of the second vertical semiconductor channel; and
the at least one annular dielectric spacer has greater lateral extent than the first memory film and the second memory film.

7. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
the first and second electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the first and second electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate; and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

8. The three-dimensional memory device of claim 3 , wherein:
the first annular dielectric spacer is present at a level of the joint-level electrically conductive layer and is not present at levels of the joint-level insulating layer and the additional joint-level electrically conductive layer; and
the second annular dielectric spacer continuously extends from a horizontal plane including a bottom surface of the joint-level electrically conductive layer to the bottom surface of the second alternating stack.

9. The three-dimensional memory device of claim 3 , wherein:
a first-tier insulating cap layer is located between the first alternating stack and the joint-level electrically conductive layer;
the first annular dielectric spacer is present at a level of the joint-level electrically conductive layer and is not present at levels of the joint-level insulating layer and the additional joint-level electrically conductive layer; and
the second annular dielectric spacer contacts a top surface of the first annular dielectric spacer, and does not directly contact the first-tier insulating cap layer.

10. The three-dimensional memory device of claim 1 , wherein:
the first annular dielectric spacer comprises a dielectric oxide of a semiconductor material of a portion of the at least one joint-level doped semiconductor portion; and
the second annular dielectric spacer comprises a material selected from a dielectric metal oxide and a silicon oxide material having a different composition from the first annular dielectric spacer.

11. The three-dimensional memory device of claim 1 , wherein an entire outer sidewall of the first annular dielectric spacer is in direct c

Assignees

• Sandisk Technologies Llc

Inventors

• Costa Xiying
• Mao Daxin
• Petti Christopher
• Lee Dana
• Lee Yao-Sheng

Classifications

• H01L27/11582

  Electricity · mapped topic

• H01L27/11524 Primary

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic