Three-dimensional memory device containing annular etch-stop spacer and method of making thereof

US9780034B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-9780034-B1
Application numberUS-201615183195-A
CountryUS
Kind codeB1
Filing dateJun 15, 2016
Priority dateMar 16, 2016
Publication dateOct 3, 2017
Grant dateOct 3, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

A method of forming a monolithic three-dimensional memory device includes forming a first alternating stack over a substrate, forming an insulating cap layer, forming a first memory opening through the insulating cap layer and the first alternating stack, forming a sacrificial pillar structure in the first memory opening, forming a second alternating stack, forming a second memory opening, forming an inter-stack memory opening, forming a memory film and a first semiconductor channel layer in the inter-stack memory opening, anisotropically etching a horizontal bottom portion of the memory film and the first semiconductor channel layer to expose the substrate at the bottom of the inter-stack memory opening such that damage to portions of the first semiconductor channel layer and the memory film located adjacent to the insulating cap layer is reduced or avoided, and forming a second semiconductor channel layer in contact with the exposed substrate in the inter-stack memory opening.

First claim

Opening claim text (preview).

What is claimed is: 1. A monolithic three-dimensional memory device, comprising: a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate; an insulating cap layer overlying the first alternating stack; a second alternating stack of second insulating layers and second electrically conductive layers overlying the insulating cap layer; and a memory stack structure extending through the second alternating stack, the insulating cap layer, and the first alternating stack and comprising a semiconductor channel and a memory film including a plurality of charge storage regions, wherein: the insulating cap layer comprises a first concave surface having a first radius of curvature, laterally surrounding the memory stack structure, and adjoined to an upper periphery of a substantially vertical sidewall of the memory stack structure; and the insulating cap layer comprises a second concave surface having a second radius of curvature that is greater than the first radius of curvature, laterally surrounding the memory stack structure, and adjoined to an upper periphery of the first concave surface. 2. The monolithic three-dimensional memory device of claim 1 , wherein the memory stacks structure contains a tapered portion adjacent to the insulating cap layer. 3. The monolithic three-dimensional memory device of claim 1 , wherein: an upper periphery of the second concave surface is adjoined to a lower periphery of a substantially vertical sidewall of the insulating cap layer; a first convex sidewall of the memory stack structure contacts the first concave sidewall of the insulating cap layer; and a second convex sidewall of the memory stack structure contacts the second concave sidewall of the insulating cap layer. 4. The monolithic three-dimensional memory device of claim 1 , further comprising an annular spacer that laterally surrounds the memory stack structure, wherein: a first convex sidewall of the annular spacer contacts the first concave sidewall of the insulating cap layer; and a second convex sidewall of the annular spacer contacts the second concave sidewall of the insulating cap layer.

Assignees

Inventors

Classifications

  • H10W20/089Primary

    using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

  • Electricity · mapped topic

  • Electricity · mapped topic

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What does patent US9780034B1 cover?
A method of forming a monolithic three-dimensional memory device includes forming a first alternating stack over a substrate, forming an insulating cap layer, forming a first memory opening through the insulating cap layer and the first alternating stack, forming a sacrificial pillar structure in the first memory opening, forming a second alternating stack, forming a second memory opening, form…
Who is the assignee on this patent?
Sandisk Technologies Llc
What technology area does this patent fall under?
Primary CPC classification H10W20/089. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 03 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).