Three-dimensional memory device containing annular etch-stop spacer and method of making thereof

Patent metadata

Field	Value
Publication number	US-9768192-B1
Application number	US-201615071575-A
Country	US
Kind code	B1
Filing date	Mar 16, 2016
Priority date	Mar 16, 2016
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

An etch-stop annular spacer can be formed around a protruding portion of a sacrificial pillar structure that fills a lower memory opening through a first insulating cap layer and through an underlying first alternating stack of first insulating layers and first spacer layers. The etch-stop layer comprises a material that is different from the material of the sacrificial pillar structure. After formation of a second insulating cap layer, a second alternating stack of second insulating layers and second spacer layers can be formed over the sacrificial pillar structure. An upper memory opening is formed though the second alternating stack by an anisotropic etch that employs the etch-stop annular spacer as an etch stop. A memory opening is formed by removing the sacrificial pillar structure underneath the upper memory opening selective to the etch-stop annular spacer. A memory stack structure without a convex protrusion can be formed in the memory opening.

First claim

What is claimed is:

1. A monolithic three-dimensional memory device, comprising:
a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate;
an insulating tier cap layer overlying the first alternating stack;
a second alternating stack of second insulating layers and second electrically conductive layers;
a memory opening extending through the second alternating stack, the insulating tier cap layer, and the first alternating stack;
a memory stack structure located within the memory opening and comprising a semiconductor channel and a memory film including a plurality of charge storage regions; and
an annular spacer located within the insulating tier cap layer and laterally surrounding the memory stack structure, wherein the annular spacer comprises a doped semiconductor material.

2. The monolithic three-dimensional memory device of claim 1 , wherein an inner sidewall of the annular spacer contacts a portion of an outer sidewall of the memory film.

3. The monolithic three-dimensional memory device of claim 2 , wherein a bottom surface of the annular spacer is vertically spaced from a bottom surface of the insulating tier cap layer.

4. The monolithic three-dimensional memory device of claim 1 , wherein the annular spacer has a horizontal bottom surface and a tapered sidewall surface.

5. The monolithic three-dimensional memory device of claim 1 , wherein the insulating tier cap layer comprises:
a first insulating cap layer having a top surface that is coplanar with a bottom surface of the annular spacer; and
a second insulating cap layer having a top surface that is coplanar with a topmost surface of the annular spacer.

6. The monolithic three-dimensional memory device of claim 1 , wherein first sidewalls of the memory opening located in a lower portion of the insulating tier cap layer are laterally offset with respect to second sidewalls of the memory opening located in the second alternating stack.

7. The monolithic three-dimensional memory device of claim 6 , wherein:
one of the first sidewalls of the memory opening extends to a horizontal plane including an interface between the insulating tier cap layer and the second alternating stack; and
one of the second sidewalls of the memory opening extends into a middle portion of the annular spacer.

8. The monolithic three-dimensional memory device of claim 1 , wherein:
the memory opening has a first horizontal ledge at an interface between the insulating tier cap layer and the second alternating stack;
the memory opening has a second horizontal ledge that contacts a horizontal surface of the annular spacer between a top surface of the annular spacer and a bottom surface of the annular spacer;
the first and second horizontal ledges extend substantially parallel to the top surface of the substrate; and
the second horizontal ledge is located closer to the top surface of the substrate than the first horizontal ledge.

9. The monolithic three-dimensional memory device of claim 1 , wherein the memory film comprises:
a blocking dielectric layer contacting a sidewall of the memory opening;
the plurality of charge storage regions located on an inner sidewall of the blocking dielectric layer; and
a tunneling dielectric layer located inside the plurality of charge storage regions.

10. The monolithic three-dimensional memory device of claim 1 , wherein:
the monolithic three-dimensional memory structure comprises a monolithic three-dimensional NAND memory device;
the first and second electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Nakamura Tadashi

Classifications

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title