Passivation scheme for pad openings and trenches

Patent metadata

Field	Value
Publication number	US-12424573-B2
Application number	US-202418652868-A
Country	US
Kind code	B2
Filing date	May 2, 2024
Priority date	Jul 14, 2017
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a group III-V layer overlying a substrate;
an interlayer dielectric (ILD) layer overlying the group III-V layer;
a conductive structure overlying the ILD layer; and
a passivation layer overlying the ILD layer and the conductive structure, and further extending through the ILD layer at a periphery of the integrated circuit to an elevation recessed relative to a top surface of the group III-V layer.

2. The integrated circuit according to claim 1 , wherein a bottom surface of the passivation layer is elevated relative to a top surface of the substrate and is recessed relative to the top surface of the group III-V layer.

3. The integrated circuit according to claim 1 , wherein the passivation layer extends through the ILD layer at a trench, which extends laterally in a closed path along the periphery of the integrated circuit.

4. The integrated circuit according to claim 1 , wherein the passivation layer has a U-shaped or V-shaped cross-sectional profile extending through the ILD layer to the elevation.

5. The integrated circuit according to claim 1 , wherein the conductive structure has a pair of outermost sidewalls facing away from each other, wherein the passivation layer has a pair of opposing sidewalls laterally between the pair of outermost sidewalls, and wherein the passivation layer is spaced from the pair of outermost sidewalls.

6. The integrated circuit according to claim 5 , wherein the pair of opposing sidewalls of the passivation layer have individual bottom edges directly contacting a top surface of the conductive structure.

7. The integrated circuit according to claim 1 , wherein the passivation layer has a lower water vapor transmission rate than the ILD layer.

8. An integrated circuit, comprising:
an interlayer dielectric (ILD) layer overlying a substrate and having a sidewall extending laterally in a closed path along an edge of the integrated circuit;
a plurality of conductive features in the ILD layer and alternatingly stacked away from the substrate; and
a passivation layer overlying the ILD layer and the plurality of conductive features, and further configured to block moisture or vapor from entering the ILD layer through the sidewall of the ILD layer.

9. The integrated circuit according to claim 8 , wherein the passivation layer curves around a top corner of the sidewall of the ILD layer, from a location directly over the ILD layer to a location recessed relative to the top corner.

10. The integrated circuit according to claim 8 , wherein the passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

11. The integrated circuit according to claim 8 , wherein the passivation layer directly contacts the sidewall of the ILD layer.

12. The integrated circuit according to claim 8 , further comprising:
a conductive pad overlying the ILD layer and underlying a pad opening; and
a dielectric layer overlying and directly contacting the conductive pad at an interface, wherein the passivation layer is configured to block moisture or vapor from migrating from the pad opening to the interface.

13. The integrated circuit according to claim 8 , further comprising:
a conductive pad overlying and directly contacting a top surface of the ILD layer, wherein the conductive pad is exposed from over the integrated circuit, and wherein the sidewall of the ILD layer extends to the substrate from the top surface of the ILD layer.

14. The integrated circuit according to claim 8 , wherein the ILD layer has an additional sidewall extending laterally in an additional closed path along the edge of the integrated circuit, and wherein the sidewall of the ILD layer and the additional sidewall of the ILD layer face each other and are lined by the passivation layer.

15. An integrated circuit, comprising:
a conductive pad overlying a substrate;
a dielectric structure between the substrate and the conductive pad and further having a sidewall in a trench, which is at a periphery of the integrated circuit and which extends to the substrate; and
a passivation layer extending along the sidewall of the dielectric structure, and further overlying and directly contacting a top surface of the conductive pad at an interface, which is laterally offset from outermost sidewalls of the conductive pad.

16. The integrated circuit according to claim 15 , wherein the passivation layer curves downward around a top corner of the conductive pad from a location directly over the conductive pad.

17. The integrated circuit according to claim 15 , wherein the passivation layer is spaced from the dielectric structure and has a pair of opposing sidewalls in the trench, and wherein the pair of opposing sidewalls have individual bottom edges recessed relative to a top surface of the substrate.

18. The integrated circuit according to claim 17 , wherein the substrate comprises a group II-VI or IV-IV semiconductor layer at the top surface of the substrate.

19. The integrated circuit according to claim 15 , wherein the passivation layer comprises a first layer and a second layer overlying the first layer, wherein the first and second layers are spaced from the sidewall of the dielectric structure and both extend through the dielectric structure at the trench, and wherein second layer extends along a sidewall of the first layer directly over the conductive pad.

20. The integrated circuit according to claim 15 , wherein the sidewall of the dielectric structure comprises silicon oxide, and wherein the passivation layer comprises aluminum oxide or polyimide.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Ming-Hong
• Yang Chun-Yi
• Huang Kun-Ming
• Chu Po-Tao
• Wang Shen-Ping
• Kuo Chien-Li

Classifications

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title