Passivation scheme for pad openings and trenches

Patent metadata

Field	Value
Publication number	US-11444046-B2
Application number	US-202017004467-A
Country	US
Kind code	B2
Filing date	Aug 27, 2020
Priority date	Jul 14, 2017
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

First claim

What is claimed is:

1. An integrated circuit comprising:
a substrate;
an interlayer dielectric (ILD) layer overlying the substrate;
a conductive pad overlying the ILD layer;
a first passivation layer overlying the ILD layer and the conductive pad, wherein the first passivation layer defines a pad opening overlying and partially exposing the conductive pad; and
a second passivation layer overlying the ILD layer, the conductive pad, and the first passivation layer, and further lining a sidewall of the first passivation layer in the pad opening, wherein the second passivation layer has a high resistance to moisture or vapor relative to the ILD layer.

2. The integrated circuit according to claim 1 , wherein the ILD layer and the first passivation layer comprise oxide, and wherein the second passivation layer comprises silicon nitride, aluminum oxide, or polyimide.

3. The integrated circuit according to claim 1 , wherein the second passivation layer has an L-shaped profile directly contacting the conductive pad and the sidewall of the first passivation layer.

4. The integrated circuit according to claim 1 , further comprising:
a plurality of peripheral pads on the ILD layer and comprising the conductive pad, wherein the peripheral pads are arranged along a boundary of the integrated circuit.

5. The integrated circuit according to claim 1 , further comprising:
a third passivation layer overlying the first and second passivation layers and lining a sidewall of the second passivation layer in the pad opening.

6. The integrated circuit according to claim 5 , wherein the third passivation layer has a lower water vapor transmission rate than the ILD layer and/or the first passivation layer.

7. The integrated circuit according to claim 1 , further comprising:
a semiconductor device on the substrate; and
a conductive interconnect structure in the ILD layer and defining a conductive path from the semiconductor device to the conductive pad.

8. An integrated circuit comprising:
a substrate;
an interlayer dielectric (ILD) layer overlying the substrate, wherein the ILD layer at least partially defines a trench, and wherein the trench extends vertically through the ILD layer from a top of the ILD layer to the substrate and further extends laterally in a closed path along an edge of the integrated circuit;
a first passivation layer overlying the ILD layer, wherein the first passivation layer lines and directly contacts a sidewall of the ILD layer in the trench; and
a second passivation layer overlying the ILD layer and the first passivation layer, wherein the second passivation layer lines the sidewall of the ILD layer in the trench and over the first passivation layer, and wherein the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

9. The integrated circuit according to claim 8 , wherein the first and second passivation layers have U-shaped or V-shaped profiles in the trench.

10. The integrated circuit according to claim 8 , further comprising:
a third passivation layer overlying the second passivation layer, wherein the third passivation layer lines the sidewall of the ILD layer in the trench and over the second passivation layer, and wherein the third passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

11. The integrated circuit according to claim 8 , further comprising:
a semiconductor device on the substrate and underlying the ILD layer, wherein the closed path surrounds the semiconductor device.

12. The integrated circuit according to claim 8 , wherein the substrate comprises a silicon layer and a group III-V layer overlying the silicon layer, and wherein the first passivation layer lines and directly contacts a sidewall of the group III-V layer.

13. The integrated circuit according to claim 8 , further comprising:
a conductive pad overlying the ILD layer, wherein the first and second passivation layers overlie the conductive pad, and wherein the second passivation layer extends through the first passivation layer to the conductive pad at a pad opening overlying the conductive pad.

14. The integrated circuit according to claim 8 , wherein the second passivation layer has a water vapor transmission rate of about 10 −6 -10 −3 grams per square meter per day (g/m 2 /day).

15. An integrated circuit comprising:
a substrate;
a semiconductor device on the substrate;
a plurality of wires and a plurality of vias alternatingly stacked over and defining a conductive path leading from the semiconductor device;
a first passivation layer overlying the wires and the vias; and
a second passivation layer overlying the first passivation layer, wherein the second passivation layer lines a sidewall of the first passivation layer and has a lower water vapor transmission rate than the first passivation layer;
wherein the second passivation layer at least partially defines a protrusion extending vertically to the substrate at a periphery of the integrated circuit.

16. The integrated circuit according to claim 15 , wherein the protrusion is ring shaped and laterally surrounds the semiconductor device and the sidewall.

17. The integrated circuit according to claim 15 , wherein the protrusion is also partially defined by the first passivation layer.

18. The integrated circuit according to claim 15 , wherein the protrusion extends through the first passivation layer.

19. The integrated circuit according to claim 15 , further comprising:
a metal structure underlying and directly contacting the first passivation layer at an interface, wherein the second passivation layer seals the interface from vapor and/or moisture, and wherein the interface is at a bottom edge of the sidewall.

20. The integrated circuit according to claim 15 , wherein the first passivation layer comprises multiple different dielectric layers, wherein the multiple different dielectric layers define individual portions of the sidewall, and wherein the individual portions are lined by the second passivation layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Ming-Hong
• Yang Chun-Yi
• Huang Kun-Ming
• Chu Po-Tao
• Wang Shen-Ping
• Kuo Chien-Li

Classifications

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title