Passivation scheme for pad openings and trenches

Patent metadata

Field	Value
Publication number	US-10312207-B2
Application number	US-201815883797-A
Country	US
Kind code	B2
Filing date	Jan 30, 2018
Priority date	Jul 14, 2017
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

First claim

What is claimed is:

1. An integrated circuit comprising:
a substrate;
an interlayer dielectric (ILD) layer covering the substrate, wherein the ILD layer at least partially defines a trench, and wherein the trench extends through the ILD layer from a top of the ILD layer to the substrate;
a conductive pad overlying the ILD layer;
a first passivation layer overlying the ILD layer and the conductive pad, wherein the first passivation layer defines a pad opening overlying the conductive pad; and
a second passivation layer overlying the ILD layer, the conductive pad, and the first passivation layer, and further lining sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench.

2. The integrated circuit according to claim 1 , wherein the first passivation layer partially defines the trench, wherein the second passivation layer directly lines additional sidewalls of the first passivation layer in the trench, and wherein the second passivation layer directly lines the sidewalls of the ILD layer in the trench.

3. The integrated circuit according to claim 1 , wherein the second passivation layer has an upper surface in the trench, and wherein the upper surface of the second passivation layer is recessed below a top surface of the second passivation layer and a top surface of the ILD layer.

4. The integrated circuit according to claim 1 , wherein the first passivation layer directly lines the sidewalls of the ILD layer in the trench, and wherein the second passivation layer lines the sidewalls of the ILD layer over the first passivation layer.

5. The integrated circuit according to claim 1 , wherein the first passivation layer has an upper surface in the trench, wherein the upper surface of the first passivation layer is recessed below a top surface of the first passivation layer and a top surface of the ILD layer, wherein the second passivation layer has an upper surface in the trench, and wherein the upper surface of the second passivation layer is recessed below a top surface of the second passivation layer and the top surface of the ILD layer.

6. The integrated circuit according to claim 1 , wherein a portion of the second passivation layer in the trench has a U-shaped or V-shaped cross-sectional profile.

7. The integrated circuit according to claim 1 , wherein the trench extends laterally in a closed path to completely enclose a central portion of the ILD layer, and to separate the central portion of the ILD layer from a peripheral portion of the ILD layer, wherein the conductive pad is on the central portion of the ILD layer, and wherein the second passivation layer extends continuously from directly over the peripheral portion of the ILD layer to the conductive pad through the trench.

8. The integrated circuit according to claim 1 , wherein the ILD layer comprises oxide, and wherein the second passivation layer comprises silicon nitride, aluminum oxide, or polyimide.

9. The integrated circuit according to claim 1 , wherein the substrate comprises:
a bulk semiconductor substrate; and
a group III-V layer covering the bulk semiconductor substrate, wherein the ILD layer covers the group III-V layer, wherein the trench extends through the group III-V layer to the bulk semiconductor substrate, and wherein the trench is partially defined by the group III-V layer.

10. An integrated circuit comprising:
a semiconductor substrate;
a group III-V layer covering the semiconductor substrate;
a semiconductor device overlying and partially defined by the group III-V layer;
an interconnect structure covering the semiconductor device and the group III-V layer, wherein the interconnect structure comprises an interlayer dielectric (ILD) layer, a plurality of wires, and a plurality of vias, wherein the wires and the vias are alternatingly stacked in the ILD layer, wherein the ILD layer and the group III-V layer at least partially define a trench, and wherein the trench extends laterally in a closed path to completely enclose the semiconductor device;
a conductive pad overlying the ILD layer and electrically coupled to the semiconductor device by the wires and the vias;
a first passivation layer overlying the ILD layer and the conductive pad, wherein the first passivation layer defines a pad opening overlying the conductive pad; and
a second passivation layer overlying the ILD layer, the conductive pad, and the first passivation layer, and further lining sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench, wherein the second passivation layer has a low permeability for water vapor relative to the ILD layer.

11. The integrated circuit according to claim 10 , wherein the first passivation layer also has a low permeability for water vapor relative to the ILD layer.

12. The integrated circuit according to claim 10 , wherein the trench separates a central portion of the ILD layer from a peripheral portion of the ILD layer, wherein the first passivation layer extends continuously from the peripheral portion of the ILD layer to the central portion of the ILD layer while lining and directly contacting the sidewalls of the ILD layer in the trench, wherein the first passivation layer partially fills the trench, wherein the second passivation layer overlies and directly contacts the first passivation layer in the trench, and wherein the second passivation layer directly contacts the conductive pad.

13. The integrated circuit according to claim 10 , wherein the trench separates a central portion of the ILD layer from a peripheral portion of the ILD layer, wherein the second passivation layer extends continuously from directly over the peripheral portion of the ILD layer to the conductive pad while lining and directly contacting the sidewalls of the ILD layer in the trench, wherein the second passivation directly contacts the first passivation layer in the trench, and wherein the second passivation layer directly contacts the conductive pad on the central portion of the ILD layer.

14. An integrated circuit comprising:
a substrate;
a dielectric layer on the substrate and at least partially defining a trench, wherein the trench extends through the dielectric layer from a top surface of the dielectric layer to a bottom surface of the dielectric layer;
a conductive pad on the dielectric layer;
a first passivation layer partially covering the conductive pad and defining a pad opening overlying and exposing the conductive pad; and
a second passivation layer covering the first passivation layer, wherein the second passivation layer partially fills and is recessed into the trench and the pad opening.

15. The integrated circuit according to claim 14 , wherein the second passivation layer directly contacts sidewalls of the dielectric layer in the trench.

16. The integrated circuit according to claim 14 , wherein the first passivation layer partially fills and is recessed into the trench.

17. The integrated circuit according to claim 14 , wherein the conductive pad is on a first side of the trench, and wherein the second passivation layer extends continuously from the conductive pad to a top-surface portion of the dielectric layer on a second side of the trench that is opposite the first side.

18. The integrated circuit according to claim 14 , further comprising:
a semiconductor device on the substrate, between the substrate and the dielectric layer;
a plurality of wires; and
a plurality of vias, wherein the wires and the vias are stacked in the dielectric layer and define a conductive path fr

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Ming-Hong
• Yang Chun-Yi
• Huang Kun-Ming
• Chu Po-Tao
• Wang Shen-Ping
• Kuo Chien-Li

Classifications

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title