Passivation scheme for pad openings and trenches

Patent metadata

Field	Value
Publication number	US-12002774-B2
Application number	US-202217940081-A
Country	US
Kind code	B2
Filing date	Sep 8, 2022
Priority date	Jul 14, 2017
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

First claim

What is claimed is:

1. An integrated circuit comprising:
a substrate;
an interlayer dielectric (ILD) layer overlying the substrate;
a conductive pad overlying the ILD layer; and
a passivation layer overlying the ILD layer and the conductive pad, and further lining a sidewall in a pad opening overlying and partially exposing the conductive pad, wherein the passivation layer has a curved portion.

2. The integrated circuit according to claim 1 , further comprising:
another passivation layer overlying the ILD layer and the conductive pad, wherein the other passivation layer defines the pad opening.

3. The integrated circuit according to claim 1 , wherein the ILD layer comprises oxide, and wherein the passivation layer comprises silicon nitride, aluminum oxide, or polyimide.

4. The integrated circuit according to claim 1 , wherein the passivation layer has an L-shaped profile directly contacting the conductive pad and the sidewall in the pad opening.

5. The integrated circuit according to claim 1 , further comprising:
another passivation layer overlying the passivation layer and lining a sidewall of the passivation layer in the pad opening.

6. The integrated circuit according to claim 5 , wherein the other passivation layer has a lower water vapor transmission rate than the ILD layer.

7. The integrated circuit according to claim 1 , further comprising:
a semiconductor device on the substrate; and
a conductive interconnect structure in the ILD layer and defining a conductive path from the semiconductor device to the conductive pad.

8. An integrated circuit comprising:
a substrate;
an interlayer dielectric (ILD) layer overlying the substrate, wherein the ILD layer at least partially defines a trench, and wherein the trench extends vertically through the ILD layer from a top of the ILD layer to the substrate and further extends laterally in a closed path along an edge of the integrated circuit; and
a passivation layer overlying the ILD layer, wherein the passivation layer lines a sidewall of the ILD layer in the trench, and wherein the passivation layer has a curved portion.

9. The integrated circuit according to claim 8 , further comprising:
another passivation layer overlying the ILD layer, wherein the other passivation layer lines and directly contacts the sidewall of the ILD layer in the trench.

10. The integrated circuit according to claim 9 , further comprising:
a conductive pad overlying the ILD layer, wherein the passivation layer and the other passivation layer overlie the conductive pad, and wherein the passivation layer extends through the other passivation layer to the conductive pad at a pad opening overlying the conductive pad.

11. The integrated circuit according to claim 8 , wherein the passivation layer has a U-shaped or V-shaped profile in the trench.

12. The integrated circuit according to claim 8 , further comprising:
another passivation layer overlying the passivation layer, wherein the other passivation layer lines the sidewall of the ILD layer in the trench and over the passivation layer, and wherein the other passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

13. The integrated circuit according to claim 8 , further comprising:
a semiconductor device on the substrate and underlying the ILD layer, wherein the closed path surrounds the semiconductor device.

14. The integrated circuit according to claim 8 , wherein the substrate comprises a silicon layer and a group III-V layer overlying the silicon layer, and wherein the trench extends into the group III-V layer.

15. An integrated circuit comprising:
a substrate;
a semiconductor device on the substrate;
an interlayer dielectric (ILD) layer overlying the semiconductor device;
a plurality of wires and a plurality of vias in the ILD layer, wherein the plurality of wires and the plurality of vias are alternatingly stacked over and define a conductive path leading from the semiconductor device; and
a passivation layer overlying the ILD layer, wherein the passivation layer lines a sidewall of the ILD layer in a trench at a periphery of the integrated circuit and further has a lower water vapor transmission rate than the ILD layer;
wherein the passivation layer at least partially defines a protrusion extending vertically to the substrate through the trench.

16. The integrated circuit according to claim 15 , wherein the protrusion is ring shaped and laterally surrounds the semiconductor device and the sidewall.

17. The integrated circuit according to claim 16 , wherein the passivation layer has a curved surface wrapping around a top corner of the ILD layer.

18. The integrated circuit according to claim 15 , further comprising:
another passivation layer overlying the wires and the vias, between the passivation layer and the ILD layer, wherein the other passivation layer has a curved surface facing and directly contacting the passivation layer, and wherein the protrusion is also partially defined by the other passivation layer.

19. The integrated circuit according to claim 15 , further comprising:
another passivation layer overlying the wires and the vias, between the passivation layer and the ILD layer; and
a metal structure underlying and directly contacting the other passivation layer at an interface, wherein the passivation layer seals the interface from vapor and/or moisture.

20. The integrated circuit according to claim 19 , wherein the passivation layer has a curved surface wrapping around a top corner of the metal structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Ming-Hong
• Yang Chun-Yi
• Huang Kun-Ming
• Chu Po-Tao
• Wang Shen-Ping
• Kuo Chien-Li

Classifications

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title