Integrated circuit device

Patent metadata

Field	Value
Publication number	US-12419042-B2
Application number	US-202318186593-A
Country	US
Kind code	B2
Filing date	Mar 20, 2023
Priority date	Jun 23, 2020
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
a substrate comprising a plurality of active regions;
a device isolation layer on the substrate, the device isolation layer defining the plurality of active regions;
a plurality of bit lines spaced apart from each other on the substrate in a first direction, the plurality of bit lines extending in a second direction crossing the first direction, each of the plurality of bit lines comprising a metal layer, an uppermost surface of the metal layer of each of the plurality of bit lines being on a first level of a first line extending in the first line on the plurality of active regions and on the device isolation layer;
a direct contact provided between a first active region among the plurality of active regions and a first bit line among the plurality of bit lines;
an inner oxide layer contacting a sidewall of the direct contact; and
a carbon-containing oxide layer contacting a sidewall of the first bit line, the carbon-containing oxide layer being separate from the inner oxide layer.

2. The integrated circuit device of claim 1 , wherein a lowermost surface of the metal layer of each of the plurality of bit lines is on a second level of a second line extending in the first line on the plurality of active regions and on the device isolation layer.

3. The integrated circuit device of claim 1 , further comprising:
a plurality of contact plugs arranged in a line along the first direction, each of the plurality of contact plugs being provided one by one between two adjacent bit lines among the plurality of bit lines; and
a plurality of conductive landing pads on the plurality of contact plugs and connected to the plurality of contact plugs,
wherein an uppermost surface of each of the plurality of conductive landing pads is on a third level of a third line extending in the first line.

4. The integrated circuit device of claim 1 , further comprising a plurality of insulating capping patterns covering the plurality of bit lines,
wherein a first height of each of the plurality of insulating capping patterns is greater than a second height of the metal layer of each of the plurality of bit lines.

5. The integrated circuit device of claim 1 , further comprising a plurality of insulating capping patterns covering the plurality of bit lines,
wherein a bottom of each of the plurality of insulating capping patterns contacts the uppermost surface of the metal layer.

6. The integrated circuit device of claim 1 , further comprising a buffer layer provided between the substrate and the metal layer, the buffer layer vertically overlapping the metal layer,
wherein the buffer layer includes a silicon nitride layer.

7. The integrated circuit device of claim 1 , further comprising:
a contact plug connected to a second active region adjacent to the first active region among the plurality of active regions, and
a gap fill insulating pattern provided between a lower portion of the contact plug and the direct contact,
wherein the inner oxide layer is spaced apart from the contact plug with the gap fill insulating pattern therebetween.

8. The integrated circuit device of claim 1 , further comprising:
a contact plug connected to a second active region adjacent to the first active region among the plurality of active regions, and
a gap fill insulating pattern provided between a lower portion of the contact plug and the direct contact,
wherein the carbon-containing oxide layer comprises a portion provided between the direct contact and the gap fill insulating pattern.

9. The integrated circuit device of claim 1 , wherein the carbon-containing oxide layer includes an SiOC layer.

10. The integrated circuit device of claim 1 , further comprising:
a contact plug connected to a second active region adjacent to the first active region among the plurality of active regions,
a gap fill insulating pattern provided between a lower portion of the contact plug and the direct contact, and
an outer insulating spacer covering the sidewall of the first bit line on the gap fill insulating pattern,
wherein at least one of the gap fill insulating pattern and the outer insulating spacer includes a silicon nitride layer.

11. The integrated circuit device of claim 1 , wherein the metal layer of each of the plurality of bit lines includes tungsten.

12. An integrated circuit device, comprising:
a substrate comprising a plurality of active regions;
a first bit line and a second bit line spaced apart from each other on the substrate in a first direction, each of the first bit line and the second bit line extending in a second direction crossing the first direction, each of the first bit line and the second bit line comprising a metal layer;
a direct contact provided between a first active region among the plurality of active regions and the first bit line;
an inner oxide layer contacting a sidewall of the direct contact; and
a carbon-containing oxide layer contacting a sidewall of the first bit line, the carbon-containing oxide layer being separate from the inner oxide layer,
wherein an uppermost surface of the metal layer of each of the first bit line and the second bit line is on a first level of a first line, and
wherein a lowermost surface of the metal layer of each of the first bit line and the second bit line is on a second level of a second line parallel to the first line.

13. The integrated circuit device of claim 12 , further comprising:
a plurality of contact plugs arranged in a line along the first direction; and
a plurality of conductive landing pads on the plurality of contact plugs and connected to the plurality of contact plugs,
wherein a first contact plug among the plurality of contact plugs is provided between the first bit line and the second bit line, and the first contact plug is connected to a second active region adjacent to the first active region among the plurality of active regions, and
wherein an uppermost surface of each of the plurality of conductive landing pads is on a third level of a third line extending in the first line.

14. The integrated circuit device of claim 12 , further comprising:
a first insulating capping pattern provided on the first bit line in a vertical direction; and
a second insulating capping pattern provided on the second bit line in the vertical direction,
wherein a first height of each of the first and second insulating capping patterns is greater than a second height of the metal layer of each of the first and second bit lines in the vertical direction.

15. The integrated circuit device of claim 12 , further comprising:
a first buffer layer provided between the substrate and the metal layer of the first bit line in a vertical direction; and
a second buffer layer provided between the substrate and the metal layer of the second bit line in the vertical direction,
wherein each of the first and second buffer layers includes a silicon nitride layer.

16. The integrated circuit device of claim 12 , further comprising:
a contact plug connected to a second active region adjacent to the first active region among the plurality of active regions, the contact plug being provided between the first bit line and the second bit line;
a gap fill insulating pattern provided between a lower portion of the contact plug and the direct contact;
a first outer insulating spacer provided between the first bit line and the contact plug; and
a second outer insulating spacer provided between the second bit line and the contact plug,
wherein each of the gap fill insulating pattern, the first outer in

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hong Jiseok
• Lee Sangho
• Park Seoryong
• Ahn Jiyoung
• Lee Kiseok
• Lee Kiseok
• Choi Yoonyoung
• Han Seunguk

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10B12/482

  Bit lines · CPC title

• H10B12/0335

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title

• H10B12/03

  Making the capacitor or connections thereto · CPC title