Semiconductor device including contact pads

Patent metadata

Field	Value
Publication number	US-9177891-B2
Application number	US-201314045648-A
Country	US
Kind code	B2
Filing date	Oct 3, 2013
Priority date	Oct 23, 2012
Publication date	Nov 3, 2015
Grant date	Nov 3, 2015

Abstract

A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of bit lines that intersect an active region on a substrate and extend in a first direction;
a contact pad disposed on the active region between adjacent bit lines among the plurality of bit lines;
a contact plug disposed on the contact pad between adjacent bit lines among the plurality of bit lines; and
a plurality of spacers disposed on sidewalls of the plurality of bit lines,
wherein an upper portion of the contact pad is interposed between adjacent spacers among the plurality of spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers among the plurality of spacers.

2. The device of claim 1 , wherein the contact pad includes an epitaxial semiconductor layer and is self-aligned with a sidewall of at least one of the plurality of spacers.

3. The device of claim 1 , wherein the contact pad has a first portion in contact with the sidewall of the at least one of the plurality of spacers.

4. The device of claim 1 , wherein the contact pad has a second portion disposed under the at least one of the plurality of spacers, wherein the second portion overlaps the at least one of the plurality of spacers in a vertical direction.

5. The device of claim 1 , wherein a bottom surface of the at least one of the plurality of spacers is disposed below a bottom surface of the plurality of bit lines.

6. The device of claim 1 , further comprising a buried insulating layer disposed between the substrate and the plurality of bit lines; and
a bit line contact interposed in the buried insulating layer and configured to electrically connect the active region with at least one of the plurality of bit lines,
wherein the contact pad has a rounded sidewall that protrudes in a second direction perpendicular to the first direction, and is in contact with the buried insulating layer.

7. A semiconductor device comprising:
a buried insulating layer disposed on a substrate;
a plurality of bit lines disposed on the buried insulating layer that extend in a first direction, the plurality of bit lines having sidewalls upon which first spacers are disposed;
a plurality of contact pads interposed in the buried insulating layer between adjacent bit lines among the plurality of bit lines, each of the plurality of contact pads having a width greater than a distance between adjacent first spacers among the plurality of spacers; and
a plurality of contact plugs respectively disposed on the plurality of contact pads between adjacent bit lines among the plurality of bit lines,
wherein the buried insulating layer includes a first recess that extends in the first direction,
wherein the plurality of contact pads are in contact with an inner wall of the first recess.

8. The device of claim 7 , further comprising an isolation layer disposed on the substrate that defines an active region of the substrate,
wherein the isolation layer includes a second recess disposed in a portion thereof not covered by the buried insulating layer,
wherein each of the plurality of contact pads is in contact with an inner wall of the second recess.

9. The device of claim 7 , wherein an upper portion of a sidewall of at least one of the plurality of contact pads is in contact with a sidewall and bottom surface of a corresponding first spacer among the plurality of spacers.

10. The device of claim 7 , further comprising a plurality of second spacers, each second spacer being disposed between at least one of the plurality of bit lines and a corresponding first spacer among the plurality of spacers,
wherein bottom surfaces of the first spacers are below bottom surfaces of the plurality of second spacers.

11. The device of claim 7 , further comprising a plurality of second spacers, each second spacer being disposed between at least one of the plurality of bit lines and a corresponding first spacer among the plurality of spacers,
wherein bottom surfaces of the first spacers are above bottom surfaces of the plurality of second spacers,
wherein each of the plurality of contact pads are spaced apart from the first spacers.

12. The device of claim 7 , wherein each of the plurality of contact pads includes an epitaxial semiconductor layer.

13. The device of claim 7 , wherein each of the plurality of contact pads includes a doped polycrystalline semiconductor layer.

14. A semiconductor device comprising:
a buried insulating layer disposed on a substrate;
a plurality of bit lines disposed on the buried insulating layer that extend in a first direction, the plurality of bit lines having sidewalls upon which first spacers are disposed;
a plurality of contact pads interposed in the buried insulating layer between adjacent bit lines among the plurality of bit lines, each of the plurality of contact pads having a width greater than a distance between adjacent first spacers; and
a plurality of contact plugs respectively disposed on the plurality of contact pads between adjacent bit lines among the plurality of bit lines,
wherein an upper portion of a sidewall of at least one of the plurality of contact pads is in contact with a sidewall and bottom surface of a corresponding first spacer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Keun-Nam
• Park Sun-Young
• Shin Soo-Ho
• Yeom Kye-Hee
• Jang Hyeon-Woo
• Jeong Jin-Won
• Cho Chang-Hyun
• Hong Hyeong-Sun

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10B12/0335

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title