Low dielectric constant insulating material in 3D memory

Patent metadata

Field	Value
Publication number	US-9721964-B2
Application number	US-201414297346-A
Country	US
Kind code	B2
Filing date	Jun 5, 2014
Priority date	Jun 5, 2014
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A memory device includes a plurality of stacks of conductive strips alternating with insulating strips. At least one of the insulating strips includes an insulating material with a dielectric constant equal to or lower than 3.6. A plurality of structures of a conductive material is arranged orthogonally over the stacks. Memory elements are disposed in interface regions at cross-points between side surfaces of the stacks and structures. The insulating strips can have equivalent oxide thicknesses EOT substantially greater than their respective physical thicknesses. The EOT can be at least 10% greater than the respective physical thicknesses. The at least one of the insulating strips can consist essentially of the insulating material with a dielectric constant equal to or lower than 3.6.

First claim

What is claimed is:

1. A memory device, comprising:
a plurality of stacks of conductive strips alternating with insulating strips, at least one of the insulating strips comprising an insulating material with a dielectric constant equal to or lower than 3.6, the plurality of stacks of conductive strips including a plurality of intermediate planes of conductive strips arranged as word lines connected to a row decoder, the plurality of intermediate planes of conductive strips being disposed between a top plane of conducting strips in the stacks and a bottom plane of conducting strips in the stacks;
a plurality of structures of a conductive material arranged orthogonally over the plurality of stacks; and
memory elements in interface regions at cross-points between side surfaces of the plurality of stacks and the plurality of structures,
wherein the insulating strips have non-simple spatial periods through the intermediate planes of conductive strips.

2. The memory device of claim 1 , wherein the insulating strips have equivalent oxide thicknesses EOT substantially greater than their respective physical thicknesses, and alternate in thickness between a first equivalent oxide thickness and a second equivalent oxide thickness greater than the first equivalent oxide thickness through the intermediate planes of conductive strips.

3. The memory device of claim 2 , wherein for insulating strips in the stack, the EOT is at least 10% greater than the respective physical thicknesses, and the second equivalent oxide thickness is greater than a thickness of the conductive strips.

4. The memory device of claim 1 , wherein the insulating material is one or more of a group consisting of P-MSQ (polymethylsilsesquioxane), SiLK, fluorine-doped oxide, carbon-doped oxide, porous oxide, and spin-on organic polymeric dielectric.

5. The memory device of claim 1 , wherein said at least one of the insulating strips consists essentially of said insulating material with a dielectric constant equal to or lower than 3.6.

6. The memory device of claim 1 , including:
a stack of linking elements separated by insulating layers, and connected to respective conductive strips in the stacks of conductive strips; and
a plurality of interlayer connectors in the stack of linking elements extending from a connector surface to respective linking elements.

7. The memory device of claim 6 , including patterned conductor lines on top of the connector surface and connected to respective interlayer connectors, the patterned conductor lines including a plurality of global bit lines coupled to sensing circuits, wherein conductive strips in the stacks of conductive strips include channels for the memory elements, and structures in the plurality of structures are arranged as word lines and string select lines including vertical gates for the memory elements.

8. The memory device of claim 6 , including patterned conductor lines on top of the connector surface, connected to respective interlayer connectors, and coupled to decoding circuits, wherein conductive strips in the stacks of conductive strips are arranged as word lines and string select lines including gates for the memory elements, and structures in the plurality of structures are arranged as vertical channels for the memory elements.

9. The memory device of claim 1 , wherein conductive strips in the stacks of conductive strips include un-doped poly silicon.

10. A memory device, comprising:
a plurality of stacks of conductive strips alternating with insulating strips, at least one of the insulating strips comprising an insulating material with a dielectric constant equal to or lower than 3.6, the plurality of stacks of conductive strips including a plurality of intermediate planes of conductive strips arranged as word lines connected to a row decoder, the plurality of intermediate planes of conductive strips being disposed between a top plane of conducting strips in the stacks and a bottom plane of conducting strips in the stacks;
a plurality of structures of a conductive material arranged orthogonally over the plurality of stacks; and
memory elements in interface regions at cross-points between side surfaces of the plurality of stacks and the plurality of structures,
wherein the memory elements include charge storage structures including one or more of a group consisting of ONO (oxide-nitride-oxide), ONONO (oxide-nitride-oxide-nitride-oxide), SONOS (silicon-oxide-nitride-oxide-silicon), BE-SONOS (bandgap engineered silicon-oxide-nitride-oxide-silicon), TANOS (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, silicon), and MA BE-SONOS (metal-high-k bandgap-engineered silicon-oxide-nitride-oxide-silicon), and
wherein the insulating strips have non-simple spatial periods through the intermediate planes of conductive strips.

11. The memory device of claim 10 , wherein said at least one of the insulating strips consists essentially of said insulating material with a dielectric constant equal to or lower than 3.6.

12. A method for manufacturing a memory device, comprising:
forming a plurality of conductive layers alternating with insulating layers on an integrated circuit substrate, at least one of the insulating layers comprising an insulating material with a dielectric constant equal to or lower than 3.6;
etching the plurality of layers to define a plurality of stacks of conductive strips alternating with insulating strips, the plurality of stacks of conductive strips including a plurality of intermediate planes of conductive strips arranged as word lines connected to a row decoder, the plurality of intermediate planes of conductive strips being disposed between a top plane of conducting strips in the stacks and a bottom plane of conducting strips in the stacks;
forming a memory layer on side surfaces of the conductive strips in the plurality of stacks;
forming a layer of a conductive material over the memory layer on the plurality of stacks; and
etching the layer of the conductive material to define a plurality of structures of the conductive material arranged orthogonally over the plurality of stacks,
wherein memory elements are disposed in interface regions at cross-points between side surfaces of the plurality of stacks and the plurality of structures,
wherein the insulating strips have non-simple spatial periods through the intermediate planes of conductive strips.

13. The method of claim 12 , wherein the insulating layers have equivalent oxide thicknesses EOT substantially greater than their respective physical thicknesses, and alternate in thickness between a first equivalent oxide thickness and a second equivalent oxide thickness greater than the first equivalent oxide thickness through the intermediate planes of conductive strips.

14. The method of claim 13 , wherein for insulating strips in the stack, the EOT is at least 10% greater than the respective physical thicknesses.

15. The method of claim 12 , wherein the insulating material is one or more of a group consisting of P-MSQ (polymethylsilsesquioxane), SiLK, fluorine-doped oxide, carbon-doped oxide, porous oxide, and spin-on organic polymeric dielectric.

16. The method of claim 12 , wherein the plurality of conductive layers alternating with insulating layers has non-simple spatial periods through the conductive layers and insulating layers in the plurality.

17. The memory device of claim 12 , wherein said at least one of the insulating layers consists essentially of said insulating material with a dielectric constant equal to or lower than 3.6.

18. The method of clai

Assignees

• Macronix Int Co Ltd

Inventors

• Lee Guan-Ru

Classifications

• H01L21/28282

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H10D64/037 Primary

  comprising charge-trapping insulators · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title