Construction of integrated circuitry and a method of forming an elevationally-extending conductor laterally between a pair of structures

US10157841B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10157841-B2
Application numberUS-201715489311-A
CountryUS
Kind codeB2
Filing dateApr 17, 2017
Priority dateApr 17, 2017
Publication dateDec 18, 2018
Grant dateDec 18, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method includes forming insulative material along the opposing sides of a conductive via and a conductive line in a vertical cross-section comprising forming a laterally-inner-insulator material comprising silicon, oxygen, and carbon laterally-outward of the opposing sides of the conductive via and the conductive line in the vertical cross-section. A laterally-intervening-insulator material comprising silicon and oxygen is formed laterally-outward of opposing sides of the laterally-inner-insulator material in the vertical cross-section. The laterally-intervening-insulator material comprises less carbon, if any, than the laterally-inner-insulator material. A laterally-outer-insulator material comprising silicon, oxygen, and carbon is formed laterally-outward of opposing sides of the laterally-intervening-insulator material in the vertical cross-section. The laterally-outer-insulator material comprises more carbon than the laterally-inner-insulator material. Elevationally-extending-conductor material is formed laterally between and along the insulative material in the vertical cross-section. Additional method aspects, including structure independent of method of fabrication, are disclosed.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of forming an elevationally-extending conductor laterally between a pair of structures, comprising: forming a pair of structures individually comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the elevationally-extending-conductive via, the conductive line and the elevationally-extending-conductive via respectively having opposing sides in a vertical cross-section; after forming said pair of structures, forming elevationally-extending-insulative material along the opposing sides of the elevationally-extending-conductive via and the conductive line in the vertical cross-section, the forming of the elevationally-extending-insulative material comprising: forming a laterally-inner-insulator material comprising silicon, oxygen, and carbon laterally-outward of the opposing sides of the elevationally-extending-conductive via and the conductive line in the vertical cross-section; forming a laterally-intervening-insulator material laterally outward of and laterally along the laterally-inner-insulator material, the laterally-intervening-insulator material comprising silicon and oxygen laterally-outward of opposing sides of the laterally-inner-insulator material in the vertical cross-section; the laterally-intervening-insulator material comprising from 0 atomic percent carbon to greater than 0 atomic percent carbon and if greater than 0 atomic percent carbon being less than an amount of atomic percent carbon in the laterally-inner-insulator material; and forming a laterally-outer-insulator material laterally outward of and laterally along the laterally-intervening-insulator material, the laterally-outer-insulator material comprising silicon, oxygen, and carbon laterally-outward of opposing sides of the laterally-intervening-insulator material in the vertical cross-section; the laterally-outer-insulator material comprising more carbon than the laterally-inner-insulator material; and forming elevationally-extending-conductor material laterally between and laterally along the elevationally-extending-insulative material in the vertical cross-section. 2. The method of claim 1 wherein the laterally-intervening-insulator material has 0 atomic percent carbon therein. 3. The method of claim 1 wherein the laterally-intervening-insulator material comprises carbon. 4. The method of claim 3 wherein the laterally-intervening-insulator material comprises at least 1.0 atomic percent carbon. 5. The method of claim 1 wherein the laterally-inner-insulator material comprises greater than 4.0 atomic percent carbon and less than 9.0 atomic percent carbon, the laterally-intervening-insulator material comprises no more than 4.0 atomic percent carbon, and the laterally-outer-insulator material comprises at least 9.0 atomic percent carbon. 6. The method of claim 5 wherein the laterally-intervening-insulator material comprises carbon. 7. The method of claim 5 wherein the laterally-outer-insulator material comprises no more than 25 atomic percent carbon. 8. The method of claim 7 wherein the laterally-outer-insulator material comprises no more than 15 atomic percent carbon. 9. The method of claim 1 wherein the laterally-inner-insulator material has k greater than 4.2 and less than 4.5, the laterally-intervening-insulator material has k no greater than 4.1, and the laterally-outer-insulator material has k of at least 4.5. 10. The method of claim 1 comprising forming the elevationally-extending-insulative material onto a substrate comprising the pair of structures; the forming of the elevationally-extending-insulative material comprising sequentially forming the laterally-inner-insulator material, the laterally-intervening-insulator material, and the laterally-outer-insulator material in situ in a deposition chamber without removing the substrate from the deposition chamber between starting to form the laterally-inner-insulator material to starting to form the laterally-outer-insulator material. 11. The method of claim 1 comprising forming the laterally-outer-insulator material directly against the laterally-intervening-insulator material. 12. The method of claim 1 comprising forming the laterally-intervening-insulator material directly against the laterally-inner-insulator material. 13. The method of claim 12 comprising forming the laterally-outer-insulator material directly against the laterally-intervening-insulator material. 14. The method of claim 1 comprising reducing lateral thickness of the laterally-outer-insulator material before forming the elevationally-extending-conductor material. 15. The method of claim 1 comprising removing the laterally-intervening-insulator material from being laterally between the pair of structures to form a pair of void spaces that individually are laterally between the laterally-inner-insulator material and the laterally-outer-insulator material in a finished circuit construction. 16. The method of claim 15 wherein at least a majority of the removing occurs after forming the conductor material. 17. The method of claim 1 comprising leaving the laterally-intervening-insulator material in a finished circuit construction. 18. The method of claim 1 wherein each of the laterally-inner-insulator material and the laterally-outer-insulator material at least as initially formed consists essentially of silicon, oxygen, carbon. 19. A construction of integrated circuitry, comprising: a pair of structures individually comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the elevationally-extending-conductive via, the conductive line and the elevationally-extending-conductive via respectively having opposing sides in a vertical cross-section; elevationally-extending-insulative material along the opposing sides of the elevationally-extending-conductive via and the conductive line in the vertical cross-section, the elevationally-extending-insulative material comprising: a laterally-inner-insulator material comprising silicon, oxygen, and carbon laterally-outward of the opposing sides of the elevationally-extending-conductive via and the conductive line in the vertical cross-section; a laterally-intervening-insulator material laterally outward of and laterally along the laterally-inner-insulator material, the laterally-intervening-insulator material comprising silicon and oxygen laterally-outward of opposing sides of the laterally-inner-insulator material in the vertical cross-section; the laterally-intervening-insulator material comprising from 0 atomic percent carbon to greater than 0 atomic percent carbon and if greater than 0 atomic percent carbon being less than an amount of atomic percent carbon in the laterally-inner-insulator material; and a laterally-outer-insulator material laterally outward of and laterally along the laterally-intervening-insulator material, the laterally-outer-insulator material comprising silicon, oxygen, and carbon laterally-outward of opposing sides of the laterally-intervening-insulator material in the vertical cross-section, the laterally-outer-insulator material comprising more carbon than the laterally-inner-insulator material; and elevationally-extending-conductor material laterally between and laterally along the elevationally-extending-insulative material in the vertical cross-section. 20. A construction of integrated circuitry, comprising: a pair of structures individually comprising an elevationally-extending-co

Assignees

Inventors

Classifications

  • in the presence of a plasma [PECVD] · CPC title

  • Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548) · CPC title

  • the material being a silicon oxide, e.g. SiO2 · CPC title

  • the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC · CPC title

  • Vias, e.g. via plugs · CPC title

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What does patent US10157841B2 cover?
A method includes forming insulative material along the opposing sides of a conductive via and a conductive line in a vertical cross-section comprising forming a laterally-inner-insulator material comprising silicon, oxygen, and carbon laterally-outward of the opposing sides of the conductive via and the conductive line in the vertical cross-section. A laterally-intervening-insulator material c…
Who is the assignee on this patent?
Micron Technology Inc
What technology area does this patent fall under?
Primary CPC classification H10P14/6922. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 18 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).