Memory device for outputting test results

Patent metadata

Field	Value
Publication number	US-12417813-B2
Application number	US-202218062843-A
Country	US
Kind code	B2
Filing date	Dec 7, 2022
Priority date	Dec 8, 2021
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

A memory device includes a memory cell array and a repair circuit configured to perform a repair operation and output a dirty signal to an external destination external to the memory device. The repair circuit further performs selecting a first redundancy address of the redundancy memory cells instead of a first fail address of the first failed memory cell, storing a first redundancy mapping for the first fail address to the first redundancy address, and in response to determining a second fail address of a second failed memory cell matches the first fail address, ignoring the first redundancy mapping, and outputting a dirty signal causing a second redundancy mapping to map the first fail address to a second redundancy address different from the first redundancy address of the redundancy memory cells.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell array comprising a plurality of memory cells arranged at intersections of a plurality of rows, and a plurality of columns and redundancy memory cells configured to repair a failed memory cell from among the memory cells; and
a repair circuit configured to perform a repair operation on the failed memory cell, and output a dirty signal to an external destination external to the memory device, the repair operation including,
selecting a first redundancy address of the redundancy memory cells instead of a first fail address of a first failed memory cell,
storing a first redundancy mapping for the first fail address to the first redundancy address, and,
in response to determining a second fail address of a second failed memory cell matches the first redundancy address,
ignoring the first redundancy mapping, and
outputting the dirty signal causing a second redundancy mapping to map the first fail address to a second redundancy address different from the first redundancy address of the redundancy memory cells.

2. The memory device of claim 1 , wherein the repair circuit is further configured to store the first fail address, the first redundancy mapping for the first fail address, and the dirty signal corresponding to the first fail address.

3. The memory device of claim 2 , wherein the repair circuit comprises an anti-fuse array.

4. The memory device of claim 2 , wherein, in response to the second fail address matching the first fail address of the first redundancy mapping, the repair circuit is further configured to activate the dirty signal corresponding to the first fail address.

5. The memory device of claim 4 , wherein the memory device is configured to transmit the activated dirty signal to a test host device external to the memory device through a data line of the memory device.

6. The memory device of claim 2 , wherein the repair circuit further is further configured to store the first fail address in correspondence with the second fail address.

7. The memory device of claim 6 , wherein the repair circuit further is further configured to generate the dirty signal by comparing the first fail address stored in the repair circuit with the second fail address.

8. The memory device of claim 6 , wherein the repair circuit further comprises a register array.

9. The memory device of claim 6 , wherein
the repair circuit comprises a content addressable memory (CAM) configured to store the first fail address of the first redundancy mapping; and
the repair circuit is further configured to,
compare the first fail address stored in the CAM with the a previously stored second fail address, and
generate the dirty signal.

10. A memory device comprising:
a memory cell array comprising a plurality of memory cells arranged at intersections of a plurality of rows and a plurality of columns, and redundancy memory cells configured to repair a failed memory cell from among the plurality of memory cells; and
a repair circuit configured to,
perform a repair operation on the failed memory cell, and output an overflow flag signal to an external destination external to the memory device, the repair operation including,
selecting a first redundancy address of the redundancy memory cells instead of a first fail address of a first failed memory cell from among the plurality of memory cells,
storing a first redundancy mapping for the first fail address to the first redundancy address, and
outputting the overflow flag signal indicating that a storage space to store a second redundancy mapping for a second fail address of a second failed memory cell from among the plurality of memory cells to a second redundancy address is insufficient.

11. The memory device of claim 10 , wherein the memory device is configured to output the overflow flag signal to a test host external to the memory device through a data line of the memory device.

12. The memory device of claim 10 , wherein the repair circuit is configured to store the first fail address.

13. The memory device of claim 12 , wherein the repair circuit further comprises an anti-fuse array configured to store the first fail address and the first redundancy mapping for the first fail address.

14. The memory device of claim 13 , wherein the repair circuit is further configured to generate the overflow flag signal in response to a new fail address that is not storable in the anti-fuse array being generated.

15. The memory device of claim 12 , wherein the repair circuit is further configured to:
store the first redundancy mapping; and
generate the overflow flag signal in response to a new fail address that is not storable in the repair circuit being generated.

16. A memory device comprising:
a memory cell array comprising a plurality of memory cells arranged at intersections of a plurality of rows and a plurality of columns, and a plurality of redundancy memory cells configured to repair a failed memory cell from among the plurality of memory cells; and
a repair circuit configured to,
perform a memory test operation on the memory cell array after performing a repair operation on the failed memory cell with a first redundancy memory cell of the plurality of redundancy memory cells, and
output a first signal to an external destination external to the memory device, the first signal being obtained as a result of the memory test operation and indicating failure of the first redundancy memory cell.

17. The memory device of claim 16 , wherein the repair circuit is further configured to transmit the first signal to a test host external to the memory device through a data line of the memory device.

18. The memory device of claim 16 , wherein the repair circuit is further configured to store one or more fail addresses obtained as a result of the memory test operation.

19. The memory device of claim 18 , wherein the repair circuit is further configured to output, to the external destination, a second signal indicating that a number of fail addresses to be stored exceeds a number of fail addresses that can be stored in the repair circuit.

20. The memory device of claim 19 , wherein the memory device is further configured to transmit the second signal to a test host external to the memory device through a data line of the memory device.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Son Jongpil

Classifications

• G11C29/18

  Address generation devices; Devices for accessing memories, e.g. details of addressing circuits · CPC title

• G11C29/785

  with redundancy programming schemes · CPC title

• G11C2029/1208

  Error catch memory · CPC title

• G11C29/789

  using non-volatile cells or latches · CPC title

• G11C29/1201

  comprising I/O circuitry · CPC title