Method and apparatus for repairing memory device

Patent metadata

Field	Value
Publication number	US-2018182467-A1
Application number	US-201715699854-A
Country	US
Kind code	A1
Filing date	Sep 8, 2017
Priority date	Dec 26, 2016
Publication date	Jun 28, 2018
Grant date	—

Abstract

A method of repairing a memory device may include collecting fail information on fail cells in a multi-block memory, classifying the fail cells into first and second types, and repairing the fail cells in the multi-block memory using one or more of a global spare memory, a local spare memory, and a common spare memory, based on the fail information.

First claim

What is claimed is:

1 . A method for repairing a memory device comprising:
collecting fail information on fail cells in a multi-block memory, the multi-block memory including a plurality of block memories; classifying the fail cells into first and second types; and repairing the fail cells in the multi-block memory using one or more of a global spare memory, a local spare memory, and a common spare memory, based on the fail information, wherein the repairing of the fail cells of the multi-block memory comprises:
preferentially assigning the global spare memory to a first fail cell having the first type in a first block memory and a second fail cell having the second type in a second block memory, when a row address or a column address of the first fail cell coincides with a corresponding address of the second fail cell having the second type in the second block memory;
updating the fail information according to the assignment of the global spare memory; and
assigning one or both of the local spare memory and the common spare memory to remaining fail cells based on the updated fail information, the remaining fail cells being fail cells to which the global spare memory has not been assigned.

2 . The method of claim 1 , wherein the collecting of the fail information comprises counting a number of fail cells in each of the block memories, and
wherein classifying the fail cells into the first and second types comprises determining whether a row address or a column address of the fail cells coincides between the block memories or within a block memory.

3 . The method of claim 1 , wherein the assigning of the global spare memory comprises preferentially selecting the second fail cell in the second block memory over a third fail cell having the second type in a third block memory, the second block memory having a number of fail cells more than the third block memory, when the row address or the column address of the first fail cell in the first block memory coincides with a corresponding address of the third fail cell in the third block memory.

4 . The method of claim 1 , wherein the updating of the fail information comprises converting a third fail cell having the second type in a third block memory into the first type, when the row address or the column address of the first fail cell in the first block memory coincides with a corresponding address of the third fail cell in the third block memory and the third fail cell has different row and column addresses from other fail cells in the third block memory.

5 . The method of claim 1 , wherein the local spare memory is preferentially assigned to fail cells having the second type in a block memory corresponding to the local spare memory.

6 . The method of claim 1 , wherein the common spare memory is preferentially assigned to fail cells in a block memory having a largest number of the remaining fail cells.

7 . The method of claim 1 , wherein the common spare memory is a first common spare memory and the local spare memory is a first local spare memory, the method further comprising switching a second common spare memory disposed adjacent to a third block memory and a fourth block memory into a second local spare memory of the third block memory, when the fail information collection result indicates that the fourth block memory has no fail cell.

8 . The method of claim 1 , wherein classifying the fail cells into the first and second types comprises:
comparing an address of a previously input fail cell to an address of a currently input fail cell; classifying the currently input fail cell into the first type when a row address and a column address of the currently input fail cell are different from a row address and a column address of the previously input fail cell; and classifying the currently input fail cell into the second type when the row address of the currently input fail cell coincides with the row address of the previously input fail cell or the column address of the currently input fail cell coincides with the column address of the previously input fail cell.

9 . An apparatus for repairing a memory device, comprising:
a global repair module suitable for receiving a signal indicative of global spare memory information and outputting a signal indicative of a global repair solution; a local repair module suitable for receiving a signal indicative of local spare memory information and outputting a signal indicative of a local repair solution; a common repair module suitable for receiving a signal indicative of common spare memory information and outputting a signal indicative of a common repair solution; a final repair module suitable for combining one or more of the global repair solution, the local repair solution, and the common repair solution and outputting a final repair solution; a controller suitable for collecting fail information on fail cells in a multi-block memory, classifying the fail cells into first and second types, controlling the global repair module to preferentially assign a global spare memory to a first fail cell having the first type in a first block memory and a second fail cell having the second type in a second block memory when a row address or a column address of the first fail cell coincides with a corresponding address of the second fail cell having the second type in the second block memory, and controlling the local repair module, the common repair module, and the final repair module to assign one or both of a local spare memory and a common spare memory to remaining fail cells based on a updated fail information, the remaining fail cells being fail cells to which the global spare memory has not been assigned; and a fail update module suitable for updating the fail information on the first and second types of the fail cells in the multi-block memory according to the assignment of the global spare memory.

10 . The apparatus of claim 9 , wherein when the row address or the column address of the first fail cell in the first block memory coincides with a corresponding address of a third fail cell in a third block memory, the controller preferentially selects the second fail cell in the second block memory over the third fail cell in the third block memory, the second block memory having a number of fail cells more than the third block memory.

11 . The apparatus of claim 9 , wherein when the row address or the column address of the first fail cell in the first block memory coincides with a corresponding address of a third fail cell having the second type in a third block memory to which no global spare memory has been assigned and the third fail cell has different row and column addresses from other fail cells in the third block memory, the controller controls the fail update module to convert the second type of the third fail cell into the first type.

12 . The apparatus of claim 9 , wherein the controller controls the local repair module to preferentially assign the local spare memory to fail cells having the second type in a block memory corresponding to the local spare memory.

13 . The apparatus of claim 9 , wherein the controller controls the common repair module to preferentially assign the common spare memory to fail cells in a block memory having a largest number of the remaining fail cells.

14 . The apparatus of claim 9 , wherein the common spare memory is a first common spare memory and the local spare memory is a first local spare memory, and
wherein the controller switches a second common spare memory disposed adjacent to a third block memory and a fourth block memory into a second local spare memory of the third blo

Assignees

• Sk Hynix Inc
• Univ Yonsei Iacf

Inventors

• Kang Sung Ho
• Kim Joo Young
• Cho Kee Won
• Lee Ha Young
• Kim Sang Doo
• Jun Hongshin
• Kim Woong Hee

Classifications

• G11C29/838

  with substitution of defective spares · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G11C29/44 Primary

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/72

  with optimized replacement algorithms · CPC title

• G11C29/4401

  for self repair · CPC title