Test method of semiconductor memory device and semiconductor memory system transferring fail address data from a volatile to a non-volatile memory array using an error-correction code engine

Patent metadata

Field	Value
Publication number	US-9747998-B2
Application number	US-201414462843-A
Country	US
Kind code	B2
Filing date	Aug 19, 2014
Priority date	Nov 29, 2013
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A test method of the semiconductor memory device including a memory cell array and an anti-fuse array includes detecting failed cells included in the memory cell array; determining a fail address corresponding to the detected failed cells; storing the determined fail address in a first region of the memory cell array; and reading the fail address stored in the first region to program the read fail address in the anti-fuse array. According to the test method of a semiconductor memory device and the semiconductor memory system, since the test operation can be performed without an additional memory for storing an address, the semiconductor memory device and the test circuit can be embodied by a small area.

First claim

What is claimed is:

1. A test method of a semiconductor memory device including a memory cell array and an anti-fuse array comprising:
detecting one or more failed cells included in the memory cell array;
determining a fail address corresponding to the detected one or more failed cells;
encoding the determined fail address using an error-correcting code (ECC) engine included in the semiconductor memory device;
storing the encoded fail address in a first region of the memory cell array;
reading the stored fail address stored in the first region;
decoding and verifying the read fail address using the ECC engine;
when the verification is successful,
programming the read fail address in the anti-fuse array; and

when the verification is not successful,
correcting the read fail address using the ECC engine, and
programming the corrected fail address in the anti-fuse array.

2. The test method of claim 1 , wherein the first region is included in a redundancy cell array.

3. The test method of claim 2 , further comprising:
performing a pin setting operation to access the first region.

4. The test method of claim 1 ,
wherein the decoding of the read fail address includes generating a decoded fail address by decoding the read fail address, and
the verifying of the read fail address includes determining whether or not an error exists in the read fail address during the decoding of the read fail address.

5. The test method of claim 1 , further comprising:
comparing data programmed in the anti-fuse array with data read from the first region to verify whether or not an error exists in the data programmed in the anti-fuse array.

6. The test method of claim 1 , further comprising:
generating a repair address using the programmed anti-fuse array; and
retesting whether failed cells included in the memory cell array are repaired using the repair address.

7. The test method of claim 1 , wherein the correcting of the read fail address comprises:
determining that the read fail address includes a correctable error, using the ECC engine; and
correcting the correctable error, using the ECC engine, when the read fail address is determined to include the correctable error.

8. A semiconductor memory system comprising:
a semiconductor memory device including a memory cell array and an anti-fuse array; and
a test circuit configured to,
detect a fail address corresponding to failed cells in the memory cell array,

the test circuit including an error-correcting code (ECC) engine configured to,
encode the detected fail address, and
control the semiconductor memory device so that the encoded fail address is stored in a redundancy cell array included in the memory cell array,

the test circuit being further configured to,
read the stored fail address,
decode and verify the read fail address using the ECC engine,
when the verification is successful,
program the read fail address in the anti-fuse array, and

when the verification is not successful,
correct the read fail address using the ECC engine, and
program the corrected fail address in the anti-fuse array.

9. The semiconductor memory system of claim 8 , wherein the test circuit is configured such that the decoding includes generating a decoded fail address by decoding the stored fail address read from the redundancy cell array using the ECC engine.

10. The semiconductor memory system of claim 9 , wherein the test circuit is configured to perform the verifying of the read fail address using the ECC engine while the read fail address is decoded.

11. The semiconductor memory system of claim 8 , wherein the test circuit is configured to perform a verify operation on data programmed in the anti-fuse array by comparing the data programmed in the anti-fuse array with data read from the redundancy cell array.

12. The semiconductor memory system of claim 8 , wherein the test circuit is configured to perform a retest on the memory cell array using the anti-fuse array in which the fail address is programmed.

13. The semiconductor memory system of claim 8 , wherein the ECC engine is further configured such that the correcting of the read fail address includes:
determining that the read fail address includes a correctable error, using the ECC engine; and
correcting the correctable error, using the ECC engine, when the read fail address is determined to include the correctable error.

14. A method of operating a semiconductor memory device test circuit comprising:
performing a first test operation by using the test circuit to detect one or more failed cells included in a memory cell array of a semiconductor memory device;
determining a fail address corresponding to the detected one or more failed cells;
receiving the determined fail address at an error-correcting code (ECC) engine included in the test circuit;
encoding the determined fail address using the ECC engine;
storing the encoded fail address in a first region of the memory cell array;
reading the stored fail address;
decoding and verifying the read fail address using the ECC engine;
when the verification is successful,
programming the read fail address in an anti-fuse array of the semiconductor memory device; and

when the verification is not successful,
correcting the read fail address using the ECC engine, and
programming the corrected fail address in the anti-fuse array.

15. The method of claim 14 , further comprising:
retesting the semiconductor memory device by using the test circuit to perform a second test operation including determining whether or not one or more fail cells are included in the memory cell array,
the second test operation being performed using a repair address,
the repair address being an address generated by the anti-fuse array based on the fail address programmed into the anti-fuse array.

16. The method of claim 14 , wherein the correcting of the read fail address comprises:
determining that the read fail address includes a correctable error, using the ECC engine; and
correcting the correctable error, using the ECC engine, when the read fail address is determined to include the correctable error.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Sua
• Kang Dongsoo
• Park Chulwoo
• Yoo Jun Hee
• Yu Hak-Soo
• Youn Jaeyoun
• Lee Sung Hyun
• Jung Jinsu
• Choi Hyojin

Classifications

• G11C17/16 Primary

  using electrically-fusible links · CPC title

• G11C29/027

  in fuses · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title