Repairable semiconductor memory device and test methods for the same

Patent metadata

Field	Value
Publication number	US-10094869-B2
Application number	US-201715650451-A
Country	US
Kind code	B2
Filing date	Jul 14, 2017
Priority date	Mar 13, 2017
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

A repair device and a semiconductor device including the same are disclosed, which relate to a technology for storing failure information in a fuse circuit during a test operation. The repair device includes a test circuit configured to test data received from a cell array in response to a test signal, and output a failure signal when a failure occurs. The repair device also includes a count circuit configured to output a counting signal by counting the failure signal, a column failure decision circuit configured to determine whether a column failure occurs in response to the counting signal, and output a write enable signal. Further, the repair device includes a fuse controller configured to output a failed column address in response to the counting signal when the write enable signal is activated, and a column fuse circuit configured to sequentially store the column address.

First claim

What is claimed is:

1. A repair device comprising:
a test circuit configured to test data received from a cell array in response to a test signal, and output a failure signal when a failure occurs;
a count circuit configured to output a counting signal by counting the failure signal;
a column failure decision circuit configured to determine whether a column failure occurs in response to the counting signal, and output a write enable signal;
a fuse controller configured to output a failed column address in response to the counting signal when the write enable signal is activated; and
a column fuse circuit configured to sequentially store the column address,
wherein the test circuit re-reads data written in the cell array, and activates the failure signal when the re-read data is different from read data.

2. The repair device according to claim 1 , wherein the count circuit includes a plurality of counters, each of which includes N bits.

3. The repair device according to claim 2 , wherein the plurality of counters are sequentially activated.

4. The repair device according to claim 2 , wherein the number of the plurality of counters corresponds to a column size of the cell array.

5. The repair device according to claim 1 , wherein the column failure decision circuit activates the write enable signal when the number of the counting signals is equal to or higher than a specific number.

6. The repair device according to claim 1 , wherein:
if the counting signal is activated in an activation state of the write enable signal, the fuse controller compares a fuse address with a repair target address, and outputs a column address when the fuse address is identical to the repair target address.

7. The repair device according to claim 1 , wherein the fuse controller receives a fuse address during a boot-up operation, and determines if a fuse of the column fuse circuit is used.

8. The repair device according to claim 1 , wherein the column fuse circuit outputs a fuse address to the fuse controller when a control signal is activated, where the fuse address indicates whether each fuse set is used.

9. The repair device according to claim 1 , wherein the column fuse circuit includes a plurality of column fuse sets configured to sequentially store the column address.

10. The repair device according to claim 9 , wherein the plurality of column fuse sets are identical to the number of counters contained in the count circuit.

11. The repair device according to claim 9 , wherein the column fuse circuit further includes:
a fuse set controller configured to sequentially store a fuse address having a failure in the plurality of column fuse sets during activation of a control signal.

12. The repair device according to claim 11 , wherein the fuse set controller outputs the fuse address stored in the plurality of column fuse sets to the fuse controller in response to the control signal.

13. The repair device according to claim 1 , further comprising:
a driver configured to output a fuse address received from the column fuse circuit to a global input/output (I/O) line when a rupture signal is activated.

14. The repair device according to claim 13 , wherein the number of the drivers corresponds to the number of column fuse sets contained in the column fuse circuit.

15. The repair device according to claim 13 , further comprising:
a fuse array configured to store an address received from the driver in an E-fuse, and output an E-fuse address to the column fuse circuit during activation of a rupture signal.

16. The repair device according to claim 1 , further comprising:
a decoder configured to output an internal address and a command signal by decoding an external address and an external command signal.

17. The repair device according to claim 1 , further comprising:
a column decoder configured to decode data of the cell array, and thus output decoding data to the test circuit.

18. A semiconductor device comprising:
a cell array configured to output cell data;
a column decoder configured to decode the cell data, and output decoding data;
a test circuit configured to test the decoding data in response to a test signal, and output a failure signal when a failure occurs;
a count circuit configured to output a counting signal by counting the failure signal;
a column failure decision circuit configured to determine whether a column failure occurs in response to the counting signal, and output a write enable signal;
a fuse controller configured to output a failed column address in response to the counting signal when the write enable signal is activated; and
a column fuse circuit configured to sequentially store the column address,
wherein the test circuit re-reads data written in the cell array, and activates the failure signal when the re-read data is different from read data.

19. The semiconductor device according to claim 18 , wherein:
the count circuit includes a predetermined number of counters corresponding to a column size of the cell array; and
the column fuse circuit includes a predetermined number of column fuse sets corresponding to the number of the counters.

20. The semiconductor device according to claim 18 , wherein a plurality of counters included the count circuit are sequentially activated.

Assignees

• Sk Hynix Inc

Inventors

• Kim Sang Hee

Classifications

• G11C29/30

  Accessing single arrays · CPC title

• G11C29/24

  Accessing extra cells, e.g. dummy cells or redundant cells · CPC title

• G11C29/4401

  for self repair · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G01R31/28 Primary

  Testing of electronic circuits, e.g. by signal tracer ({EMC, EMP or similar testing of electronic circuits G01R31/002;} testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers {or computer components} G06F11/00; checking static stores for correct operation G11C29/00 {; testing receivers or transmitters of transmission systems H04B17/00}) · CPC title