Semiconductor memory devices and methods of operating the same

Patent metadata

Field	Value
Publication number	US-9953725-B2
Application number	US-201615395213-A
Country	US
Kind code	B2
Filing date	Dec 30, 2016
Priority date	Feb 29, 2012
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A method of operating a semiconductor memory device is provided. In a method of operating a semiconductor memory device including a memory cell array which includes a plurality of bank arrays, memory cells in a first region of the memory cell array are tested to detect one or more failed cells in the first region, a fail address corresponding to the detected one or more failed cells is determined and the determined fail address is stored in a second region different from the first region, in the memory cell array.

First claim

What is claimed is:

1. A method of operating a semiconductor memory device including a memory cell array that includes a plurality of bank arrays, the method comprising:
testing memory cells in a first region of the memory cell array including the plurality of bank arrays;
determining a fail address corresponding to a memory cell that fails the test; and
storing the determined fail address in a second region in the memory cell array, the second region different from the first region,
wherein the memory cells in the first region are connected to a plurality of word-lines,
the memory cells in the first region are tested on word-line by word-line basis for each of a plurality of test items,
each test result for each of the test items is transferred to the second region, and
each test result for each of the test items is accumulated in the second region and the failed cell is detected based on the accumulated test results.

2. The method of claim 1 , wherein the determined fail address is stored in the second region in a form of a look-up table.

3. The method of claim 1 , wherein storing the determined fail address in the second region comprises:
storing the determined fail address in the second region redundantly.

4. The method of claim 1 , wherein storing the determined fail address in the second region comprises:
encoding the determined fail address; and
storing the encoded fail address redundantly in the second region, and
wherein the determined fail address is encoded by an error correction circuit included in the semiconductor memory device.

5. The method of claim 1 , further comprising:
reading the fail address stored in the second region to program the fail address in an anti-fuse array included in the semiconductor memory device.

6. The method of claim 5 , wherein storing the determined fail address in the second region comprises:
encoding the determined fail address and
storing the encoded fail address redundantly in the second region,
wherein reading the fail address stored in the second region comprises:
reading the encoded fail addresses stored redundantly in the second region;
performing a majority voting on the encoded fail addresses to select an encoded fail address indicated by a majority vote; and
decoding the selected fail address.

7. The method of claim 1 ,
wherein, when the test on the memory cells in the first region for a plurality of test items is completed,
each test result for each of the test items is accumulated in the second region,
then, memory cells in the second region are tested,
wherein when each of the test items is not associated with a refresh period of the semiconductor memory device while the memory cells in the first region are being tested,
the memory cells in the first region are refreshed with a first refresh period longer than a standard refresh period, and
the memory cells in the second region are refreshed with a second refresh period equal to or shorter than the standard refresh period, and
wherein the memory cells in the first region and the memory cells in the second region provide a different reliability.

8. The method of claim 1 ,
wherein, when the test on the memory cells in the first region for a plurality of test items is completed,
each test result for each of the test items is accumulated in the second region,
then, memory cells in the second region are test,
wherein when one of the test items is associated with a refresh period of the semiconductor memory device while the memory cells in the first region are being tested,
the memory cells in the first region are refreshed with a refresh period required by the test item associated with the refresh period of the semiconductor memory device, and
wherein the memory cells in the first region and the memory cells in the second region provide a different reliability.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ryu Ye-Sin
• Cha Sang-Uhn
• Chung Hoi-Ju
• Cho Seong-Jin

Classifications

• G11C29/4401

  for self repair · CPC title

• G11C29/56004

  Pattern generation · CPC title

• G11C29/785

  with redundancy programming schemes · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C2029/5606

  Error catch memory · CPC title