Kinetic inductance devices, methods for fabricating kinetic inductance devices, and articles employing the same

Patent metadata

Field	Value
Publication number	US-12376501-B2
Application number	US-202117923995-A
Country	US
Kind code	B2
Filing date	May 7, 2021
Priority date	May 11, 2020
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

Superconducting integrated circuits and methods of forming these circuits are discussed. One superconducting integrated circuit has a substrate and a control device formed by a layer of high kinetic inductance material overlying the substrate. The control device has a loop of material, electrical connections between the loop of material and a power line, a coupling element connected to the loop of material, a pair of Josephson junctions that interrupt the loop of material, and an energy storage element connected to the loop of material. An alternative superconducting integrated circuit has a kinetic inductance device formed in a high kinetic inductance layer. The device has a compound Josephson junction structure with two parallel current paths with respective Josephson junctions, a loop of material connected to the compound Josephson junction structure, and a coupling structure. The circuit also has an additional device that couples to the coupling structure.

First claim

The invention claimed is:

1. A superconducting integrated circuit comprising:
a first kinetic inductance layer comprising high kinetic inductance material, the first kinetic inductance layer comprising a kinetic inductance device, the kinetic inductance device comprising:
a body portion comprising a length and a width;
a Josephson junction interrupting the body portion spaced along the length of the body portion, the Josephson junction comprising a restriction having a width that is less than the width of the body portion; and
a first coupler; and the superconducting integrated circuit further comprising:

an additional device comprising a second coupler that couples the additional device to the first coupler of the kinetic inductance device.

2. The superconducting integrated circuit of claim 1 , wherein the body portion comprises a compound Josephson junction structure comprising two parallel current paths interrupted by respective Josephson junctions, each Josephson junction comprising a restriction in the high kinetic inductance material of the first kinetic inductance layer.

3. The superconducting integrated circuit of claim 2 , wherein the kinetic inductance device further comprises an energy storage element that extends from the compound Josephson junction structure.

4. The superconducting integrated circuit of claim 1 , wherein the kinetic inductance device comprises one of a qubit, an inductance tuner, a coupler, a superconducting quantum interference device (SQUID) switch, and a digital to analog converter.

5. The superconducting integrated circuit of claim 1 , wherein the additional device comprises a qubit.

6. The superconducting integrated circuit of claim 1 , wherein the superconducting integrated circuit comprises one or more additional layers that are distinct from the first kinetic inductance layer, the one or more additional layers comprising the additional device.

7. The superconducting integrated circuit of claim 6 , wherein the one or more additional layers are in one or more separate planes from a plane in which the first kinetic inductance layer resides.

8. The superconducting integrated circuit of claim 7 , wherein the one or more additional layers comprise a second layer of high kinetic inductance material having a thickness that is less than the thickness of the first kinetic inductance layer.

9. A method of forming a superconducting integrated circuit comprising:
forming a kinetic inductance device in a first kinetic inductance layer, the first kinetic inductance layer comprising a high kinetic inductance material, the kinetic inductance device comprising:
a body portion comprising a length and a width;
a Josephson junction interrupting the body portion spaced along the length of the body portion, the Josephson junction comprising a restriction having a width that is less than the width of the body portion; and
a first coupling structure; and the method further comprising:

forming a second device such that the second device is coupled to the first coupling structure.

10. The method of claim 9 , wherein forming a kinetic inductance device includes:
depositing the first kinetic inductance layer to directly or indirectly overlie at least a portion of a substrate; and then
patterning the first kinetic inductance layer.

11. The method of claim 9 , wherein forming a kinetic inductance device includes:
depositing a resist layer to overlie a substrate;
patterning the resist layer;
depositing the first kinetic inductance layer after patterning the resist layer; and
removing at least a portion of the resist layer after depositing the first kinetic inductance layer.

12. The method of claim 9 , wherein forming the kinetic inductance device comprises forming the kinetic inductance device having a compound Josephson junction structure comprising two parallel current paths interrupted by respective Josephson junctions, each Josephson junction comprising a restriction in the high kinetic inductance material of the first kinetic inductance layer.

13. The method of claim 12 , wherein forming the kinetic inductance device further comprises forming an energy storage element extending from the compound Josephson junction structure.

14. The method of claim 9 , wherein forming the kinetic inductance device comprises forming one of a qubit, an inductance tuner, a coupler, a superconducting quantum interference device (SQUID) switch, and a digital to analog converter.

15. The method of claim 9 , wherein forming the second device comprises forming a qubit.

16. The method of claim 9 , wherein forming the second device comprises:
depositing one or more second layers directly or indirectly overlying at least a portion of a substrate, at least one of the one or more second layers comprising a superconducting material; and
patterning the one or more second layers to form the second device.

17. The method of claim 13 , wherein depositing one or more second layers comprises depositing a second layer of high kinetic inductance material having a thickness that is less than the thickness of the first kinetic inductance layer.

18. The method of claim 9 , wherein forming the kinetic inductance device comprises forming the kinetic inductance device directly or indirectly overlying at least a portion of a substrate.

19. The method of claim 18 , wherein forming a first kinetic inductance layer directly or indirectly overlying at least a portion of the substrate comprises depositing the first kinetic inductance layer directly on the substrate, and wherein forming a second device comprises forming the second device directly on the substrate.

20. The method of claim 9 , wherein forming a second device comprises forming the second device directly or indirectly overlying at least a portion of the first kinetic inductance layer.

21. The method of claim 9 , wherein forming a kinetic inductance device in a first kinetic inductance layer comprises forming the kinetic inductance device directly or indirectly overlying at least a portion of the second device.

Assignees

• D Wave Systems Inc
• 1372934 B C Ltd

Inventors

• Swenson Loren J

Classifications

• H10N60/85

  Superconducting active materials · CPC title

• H10N69/00

  Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00 · CPC title

• H10N60/0912

  of Josephson-effect devices · CPC title

• H10N60/805 Primary

  for Josephson-effect devices · CPC title

• G06N10/40

  Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title