Double-masking technique for increasing fabrication yield in superconducting electronics

Patent metadata

Field	Value
Publication number	US-9136457-B2
Application number	US-201313771330-A
Country	US
Kind code	B2
Filing date	Feb 20, 2013
Priority date	Sep 20, 2006
Publication date	Sep 15, 2015
Grant date	Sep 15, 2015

Abstract

An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.

First claim

What is claimed is:

1. An integrated circuit having Josephson junctions, comprising:
a Josephson junction trilayer comprising an upper superconductor, an insulating layer, and a lower superconductor, the insulating layer being between the upper superconductor and the lower superconductor;
an adhesion layer formed directly on top of the upper superconductor; and
a resist layer formed directly on top of the adhesion layer,
the resist being patterned and developed, exposing portions of the adhesion layer through the patterned and developed resist layer, and the exposed portions of the adhesion layer being etched through the upper superconductor layer to expose the insulating layer; and
portions of the lower superconducting layer under the exposed portions of the insulating layer being anodized to selectively form Josephson junction circuit elements having submicron feature sizes under remaining portions of the adhesion layer and the resist layer, wherein the anodized portions of the lower superconductor form a layer of anodized superconductor on all sidewalls of the upper superconductor and insulating layer, and undergo a volumetric increase with respect to the non-anodized portions under remaining portions of the resist layer, the volumetric increase causing local stresses which are insufficient to cause substantial peeling of the resist layer on the adhesion layer and are sufficient to cause peeling of at least a portion of the resist layer directly on the upper superconductor adjacent to the anodized portions of the lower superconductor layer.

2. The integrated circuit according to claim 1 , wherein the adhesion layer comprises silicon dioxide.

3. The integrated circuit according to claim 1 , wherein the resist is patterned with submicron resolution.

4. The integrated circuit according to claim 1 , wherein the Josephson junction trilayer comprises a niobium-based superconductor.

5. The integrated circuit according to claim 1 , wherein the Josephson junction trilayer comprises a lower layer of niobium, an insulating layer comprising aluminum oxide, and an upper layer of niobium.

6. The integrated circuit according to claim 1 , wherein the adhesion layer comprises a dielectric.

7. The integrated circuit according to claim 1 , wherein the resist comprises at least one of an electron beam exposed resist and a photoresist.

8. The integrated circuit according to claim 1 , wherein the adhesion layer is formed by chemical vapor deposition with a layer thickness of between about 5-300 nm.

9. The integrated circuit according to claim 1 , wherein the adhesion layer is formed by a sputtering process with a layer thickness of between about 5-300 nm.

10. The integrated circuit according to claim 1 , wherein the Josephson junction circuit elements comprise at least two separately operating Josephson junctions.

11. An integrated circuit having Josephson junctions, comprising:
a Josephson junction trilayer comprising an upper superconductor, an intervening insulating layer, and a lower superconductor;
an adhesion layer formed directly on top of the upper superconductor;
a resist layer formed directly on top of the adhesion layer, the resist being patterned and developed, exposing portions of the adhesion layer through the patterned and developed resist layer, and the exposed portions of the adhesion layer being etched through the upper superconductor layer to expose the insulating layer; and
portions of the lower superconducting layer beneath the exposed portions of the insulating layer being anodized, to selectively form Josephson junction circuit elements having submicron features size under remaining intact portions of the adhesion layer and the resist layer and having a layer of anodized superconductor on all sidewalls of the upper superconductor layer and insulating layer,
wherein the anodized portions of the lower superconductor are volumetrically increased with respect to the non-anodized portions under remaining intact portions of the resist layer, to induce stresses in the adhesion layer and the resist layer adjacent to the anodized portions,
wherein the resist layer is susceptible to a failure of adhesion and peeling under the induced stresses if applied directly to the upper superconductor, and the adhesion layer formed between the resist layer and the upper superconductor being effective to substantially prevent peeling of the resist layer from the stresses, such that adjacent portions of the adhesion layer or resist layer to the anodized portions of the lower superconductor layer remain substantially without peeling,
the exposed portions of the insulating layer and the anodized portions of the lower superconductor layer being removed to expose the lower superconductor layer.

12. The integrated circuit according to claim 11 , wherein the lower superconductor of the Josephson junction trilayer is formed on a silicon substrate and the adhesion layer comprises silicon dioxide.

13. The integrated circuit according to claim 11 , wherein the Josephson junction circuit elements comprise at least two separately operating Josephson junctions having submicron feature sizes.

14. The integrated circuit according to claim 11 , wherein the Josephson junction trilayer comprises a niobium-based superconductor.

15. The integrated circuit according to claim 1 , wherein the Josephson junction trilayer comprises a lower layer of niobium, an insulating layer comprising aluminum oxide, and an upper layer of niobium.

16. The integrated circuit according to claim 1 , wherein the adhesion layer comprises a dielectric and the resist comprises at least one of an electron beam exposed resist and a photoresist.

17. The integrated circuit according to claim 1 , wherein the adhesion layer is formed by chemical vapor deposition or sputtering with a layer thickness of between about 5-300 nm.

18. An integrated circuit having Josephson junctions, comprising:
a Josephson junction trilayer comprising an upper superconductor, an intervening insulating layer, and a lower superconductor;
an adhesion layer directly on top of the upper superconductor;
a patterned and developed resist layer directly on top of the adhesion layer, exposing portions of the insulating layer through etched portions of the adhesion layer corresponding to absent portions of the patterned and developed resist layer, wherein portions of the lower superconducting layer beneath the exposed portions of the insulating layer have a volumetric increase as a result of selective anodization, forming a layer of anodized superconductor on all sidewalls of the upper superconductor and intervening insulating layer, and Josephson junction circuit elements under remaining intact portions of the adhesion layer and the resist layer, portions of the adhesion layer or resist layer adjacent to the anodized portions of the lower superconductor layer being locally stressed from the selective anodization and being substantially unpeeled,
formed by a process comprising:
providing a substrate, having the Josephson junction trilayer thereon, the upper superconducting layer being directly covered by an intermediate layer comprising a dielectric having a thickness of at least 5 nm, which in turn is directly covered by a resist layer;
selectively patterning portions of the resist layer in dependence on an irradiation pattern, and developing the pattered portions of the resist layer to expose portions of the intermediate layer;
etching the exposed portions of the intermediate layer and underlying portions of the upper superconducting layer, substant

Assignees

• Hypres Inc

Inventors

• Tolpygo Sergey K

Classifications

• H01L39/2493

  Electricity · mapped topic

• H01L39/025 Primary

  Electricity · mapped topic

• H10N69/00 Primary

  Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00 · CPC title

• H10N60/0884

  Treatment of superconductor layers by irradiation, e.g. ion-beam, electron-beam, laser beam or X-rays · CPC title

• H10N60/0912

  of Josephson-effect devices · CPC title