Systems and methods for fabrication of superconducting integrated circuits

Patent metadata

Field	Value
Publication number	US-9490296-B2
Application number	US-201514589574-A
Country	US
Kind code	B2
Filing date	Jan 5, 2015
Priority date	Feb 27, 2009
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.

First claim

We claim:

1. An integrated circuit comprising:
a substrate;
a Josephson junction carried by the substrate wherein the Josephson junction is comprised of a first electrode, a second electrode, and an electrically insulative layer interposed between the first and the second electrodes, and wherein the first and the second electrodes are each formed of a material that superconducts at or below a critical temperature;
a first planarized dielectric layer carried by the Josephson junction; and
a metal layer carried by the first planarized dielectric layer, wherein the metal layer includes at least one electrical current path that superconducts at or below a critical temperature;
a superconducting via that superconductingly electrically couples at least one electrical current path from the metal layer with the first electrode of the Josephson junction, wherein the superconducting via comprises a hole extending through the dielectric layer that is at least partially filled with a material that is superconducting at or below a critical temperature; and
a second planarized dielectric layer interposed between the Josephson junction and the substrate.

2. The integrated circuit of claim 1 wherein the at least one electrical current path is comprised of at least one material selected from the group consisting of: niobium, aluminum, zinc, tin, and lead.

3. The integrated circuit of claim 1 wherein the superconducting via has a width that is less than 1 micrometer.

4. The integrated circuit of claim 1 , further comprising:
a resistor.

5. The integrated circuit of claim 4 wherein the resistor comprises platinum.

6. The integrated circuit of claim 4 wherein the resistor is carried by the second planarized dielectric layer.

7. The integrated circuit of claim 6 wherein the resistor is thermally conductively coupled to the substrate.

8. The integrated circuit of claim 4 , further comprising:
a fin thermally conductively coupled to the resistor.

9. A superconducting integrated circuit comprising:
a substrate;
a resistor carried by the substrate;
a first trilayer carried by the substrate wherein the first trilayer comprises a first electrode that superconducts at or below a critical temperature, a second electrode that superconducts at or below a critical temperature, and a first electrically insulative layer interposed between the first and the second electrodes wherein the first electrode of the first trilayer is electrically coupled to the resistor;
a second trilayer that is carried by the substrate wherein the second trilayer comprises a third electrode that superconducts at or below a critical temperature, a fourth electrode that superconducts at or below a critical temperature, and a second electrically insulative layer interposed between the third and the fourth electrodes and wherein the third electrode of the second trilayer is electrically coupled to the resistor; and
a dielectric layer carried by the substrate wherein the dielectric layer does not cover at least a portion of the resistor and wherein the first and the third electrodes each form a respective strap contact with the resistor.

10. The superconducting integrated circuit of claim 9 wherein the resistor comprises platinum.

11. The superconducting integrated circuit of claim 9 , further comprising:
a dielectric layer carried by the substrate wherein the dielectric layer covers at least a portion of the resistor;
a first via formed through the dielectric layer wherein the first electrode of the first trilayer is electrically coupled to the resistor through the first via; and
a second via formed through the dielectric layer wherein the third electrode of the second trilayer is electrically coupled to the resistor through the second via.

Assignees

• D Wave Systems Inc

Inventors

• Ladizinsky Eric
• Rose Geordie
• Hilton Jeremy P
• Dantsker Eugene
• Oh Byong Hyop

Classifications

• Y10S977/723

  On an electrically insulating substrate · CPC title

• Y10S977/707

  having different types of nanoscale structures or devices on a common substrate · CPC title

• Y10S977/943

  Information storage or retrieval using nanostructure · CPC title

• B82Y10/00 Primary

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H10D1/474

  comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides · CPC title