Trilayer josephson junction structure with small air bridge and no interlevel dielectric for superconducting qubits

Patent metadata

Field	Value
Publication number	US-9564573-B1
Application number	US-201514749115-A
Country	US
Kind code	B1
Filing date	Jun 24, 2015
Priority date	Apr 30, 2015
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A technique relates to a trilayer Josephson junction structure. A dielectric layer is on a base electrode layer that is on a substrate. A counter electrode layer is on the dielectric layer. First and second counter electrodes are formed from the counter electrode layer. First and second dielectric layers are formed from the dielectric layer. First and second base electrodes are formed from base electrode layer. The first counter electrode, first dielectric layer, and first base electrode form a first stack. The second counter electrode, second dielectric layer, and second base electrode form a second stack. A shunting capacitor is between first and second base electrodes. An ILD layer is deposited on the substrate, the first and second counter electrodes, and the first and second base electrodes. A contact bridge connects the first and second counter electrodes. An air gap is formed underneath the contact bridge by removing ILD.

First claim

What is claimed is:

1. A method of forming a trilayer Josephson junction structure, the method comprising:
depositing a dielectric layer on a base electrode layer, wherein the base electrode layer is deposited on a substrate;
depositing a counter electrode layer on the dielectric layer;
forming a first counter electrode and a second counter electrode from the counter electrode layer;
forming a first dielectric layer and a second dielectric layer from the dielectric layer;
forming a first base electrode and a second base electrode from the base electrode layer, wherein the first counter electrode, the first dielectric layer, and the first base electrode form a first stack, wherein the second counter electrode, the second dielectric layer, and the second base electrode form a second stack, and wherein a shunting capacitor is formed between the first base electrode and the second base electrode;
depositing conformally an inter-level dielectric layer on a top surface of the substrate, the first and second counter electrodes, and the first and second base electrodes;
forming a contact bridge connecting the first counter electrode and the second counter electrode, after planarizing the inter-level dielectric layer to expose tops of the first and second counter electrodes; and
forming an air gap underneath the contact bridge by removing the inter-level dielectric layer.

2. The method of claim 1 , wherein the inter-level dielectric layer is at least one of an oxide, polysilicon, nitride, and polymeric material.

3. The method of claim 1 , wherein the air gap underneath the contact bridge vertically extends between the contact bridge and the substrate.

4. The method of claim 1 , wherein the air gap underneath the contact bridge horizontally extends between the first counter electrode and the second counter electrode.

5. The method of claim 1 , wherein the air gap underneath the contact bridge horizontally extends between the first base electrode and the second base electrode.

6. The method of claim 1 , wherein the first dielectric layer and the second dielectric layer include an oxide.

7. The method of claim 1 , wherein the first dielectric layer and the second dielectric layer include at least one of hafnium oxide, aluminum oxide, and niobium nitride.

8. The method of claim 1 , wherein the first base electrode and the second base electrode include at least one of niobium, titanium nitride, aluminum, and niobium nitride; and
wherein the first counter electrode and the second counter electrode include at least one of niobium, titanium nitride, aluminum, and niobium nitride.

9. The method of claim 1 , wherein the second stack is a qubit tunnel junction.

10. The method of claim 1 , wherein the first base electrode and the second base electrode are interdigitated electrodes on the substrate.

Assignees

• IBM

Inventors

• Chang Josephine B
• Gibson Gerald W
• Ketchen Mark B

Classifications

• H01L39/2493 Primary

  Electricity · mapped topic

• H10D1/68

  Capacitors having no potential barriers · CPC title

• H10N60/805

  for Josephson-effect devices · CPC title

• H10N60/12 Primary

  Josephson-effect devices · CPC title

• H10N69/00 Primary

  Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00 · CPC title