Package core assembly and fabrication methods

Patent metadata

Field	Value
Publication number	US-12374611-B2
Application number	US-202117227837-A
Country	US
Kind code	B2
Filing date	Apr 12, 2021
Priority date	Nov 27, 2019
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

First claim

What is claimed is:

1. A semiconductor device assembly, comprising:
a silicon core structure, comprising:
a first side opposing a second side;
a first via comprising a first via surface that defines an opening extending through the silicon core structure from the first side to the second side; and
a first pocket formed in the silicon core structure, the first pocket comprising a first plurality of pocket walls that define a first opening in the silicon core structure;

a first conductive interconnection formed in the first via and having a surface exposed at the first side and the second side;
a capacitor disposed in the first pocket and coupled to a second conductive interconnection exposed at the first side or the second side; and
an insulating layer disposed over and in contact with the first side, the second side, the first via surface, and the first plurality of pocket walls, wherein a single material of the insulating layer surrounds all surfaces of the capacitor in the first opening defined by the first plurality of pocket walls and forming an intermediate layer between the first conductive interconnection and the first via surface, the insulating layer disposed within the opening of the first pocket and between a periphery of the capacitor and each of the first plurality of pocket walls, wherein all surfaces of the capacitor are in contact with the insulating layer and the insulating layer is the only insulating layer used to support the capacitor.

2. The semiconductor device assembly of claim 1 , further comprising an oxide layer formed between the silicon core structure and the insulating layer.

3. The semiconductor device assembly of claim 2 , wherein the oxide layer comprises a thermal oxide.

4. The semiconductor device assembly of claim 1 , wherein the capacitor comprises silicon or ceramic.

5. The semiconductor device assembly of claim 1 , wherein the capacitor has a thickness substantially equal to a thickness of the silicon core structure.

6. The semiconductor device assembly of claim 1 , wherein the capacitor is a decoupling capacitor.

7. The semiconductor device assembly of claim 1 , wherein the capacitor is a trench capacitor.

8. The semiconductor device assembly of claim 1 , wherein the insulating layer has a thickness ranging from about 30 μm to about 100 μm between surfaces of the capacitor and sidewalls of the first pocket.

9. The semiconductor device assembly of claim 1 , wherein the insulating layer comprises an epoxy resin material.

10. The semiconductor device assembly of claim 9 , wherein the epoxy resin material comprises silica particles ranging in size between about 80 nm and about 1 μm.

11. The semiconductor device assembly of claim 1 , further comprising:
a second plurality of vias comprising a second via surface that defines a second opening extending through the silicon core structure from the first side to the second side;
a second pocket formed in the silicon core structure and disposed between one or more of the second plurality of vias formed on a first side of the second pocket and one more of the second plurality of vias disposed on a second side of the second pocket, the second pocket comprising a second plurality of pocket walls that define an opening in the silicon core structure; and
an inductor comprising:
a plurality of third conductive interconnections formed in the second plurality of vias, each of the third conductive interconnections having a surface exposed at the first side and the second side of the silicon core structure;
a magnetic core embedded in the second pocket; and
redistribution connections formed between one or more of the second plurality of vias formed on a first side of the second pocket and one more second vias disposed on a second side of the second pocket.

12. The semiconductor device assembly of claim 1 , further comprising
a second plurality of vias comprising a second via surface that defines a second opening extending through the silicon core structure from the first side to the second side; and an inductor comprising:
a plurality of third conductive interconnections formed in the second plurality of vias, each of the third conductive interconnections having a surface exposed at the first side and the second side of the silicon core structure; and
redistribution connections formed between the plurality of third conductive interconnections.

13. The semiconductor device assembly of claim 1 , further comprising a heat exchanger coupled to the silicon core structure, wherein the heat exchanger is coupled to the silicon core structure via an interfacial layer.

14. The semiconductor device assembly of claim 1 , further comprising a heat exchanger coupled to the silicon core structure, wherein the heat exchanger is coupled directly coupled to the silicon core structure.

15. A semiconductor device assembly, comprising:
a silicon core structure having a thickness less than 1000 μm, the silicon core structure comprising:
a first side opposing a second side;
a via comprising a via surface that defines an opening extending through the silicon core structure from the first side to the second side;
a pocket formed in the silicon core structure and extending through the silicon core structure from the first side to the second side, the pocket comprising a plurality of pocket walls that define an opening in the silicon core structure; and
a passivating layer formed on all surfaces of the silicon core structure;

a first conductive interconnection formed in the via and having a surface exposed at the first side and the second side;
a capacitor disposed in the pocket and coupled to a second conductive interconnection exposed at the first side or the second side; and
an insulating layer disposed over and in contact with the first side, the second side, the via surface, and the plurality of pocket walls, wherein a single material of the insulating layer surrounds all surfaces of the capacitor in the opening defined by the plurality of pocket walls and forming an intermediate layer between the first conductive interconnection and the via surface, the insulating layer disposed over the opening and between a periphery of the capacitor and each of the plurality of pocket walls, and comprising an epoxy resin having silica particles disposed therein, wherein all surfaces of the capacitor are in contact with the insulating layer and the insulating layer is the only insulating layer used to support the capacitor.

16. The semiconductor device assembly of claim 15 , wherein the passivating layer comprises a thermal oxide layer formed between the silicon core structure and the insulating layer.

17. The semiconductor device assembly of claim 15 , wherein the capacitor comprises silicon or ceramic.

18. The semiconductor device assembly of claim 17 , wherein the capacitor has a thickness substantially equal to or less than a thickness of the silicon core structure.

19. The semiconductor device assembly of claim 17 , wherein the capacitor is a decoupling capacitor.

20. The semiconductor device assembly of claim 17 , wherein the capacitor is a trench capacitor.

21. The semiconductor device assembly of claim 15 , wherein the insulating layer has a thickness ranging from about 30 μm to about 100 μm between surfaces of the capacitor and sidewalls of the pocket.

22. The semiconductor device assembly of claim 15 , wherein the silicon core structure comprises a crystalline silicon substrate.

23. A s

Assignees

• Applied Materials Inc

Inventors

• Chen Han-Wen
• Verhaverbeke Steven
• Park Giback
• Cho Kyuil
• Leschkies Kurtis
• Gouk Roman
• Buch Chintan
• Dicaprio Vincent
• Stonas Bernhard
• Delmas Jean

Classifications

• H10W70/698

  Semiconductor materials that are electrically insulating, e.g. undoped silicon · CPC title

• H10W70/635 Primary

  Through-vias · CPC title

• H10W70/095 Primary

  of vias therein · CPC title

• H10W70/66

  Conductive materials thereof · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title