Substrate patterning using hybrid laser scribing and plasma etching processing schemes

Patent metadata

Field	Value
Publication number	US-8980727-B1
Application number	US-201414272111-A
Country	US
Kind code	B1
Filing date	May 7, 2014
Priority date	May 7, 2014
Publication date	Mar 17, 2015
Grant date	Mar 17, 2015

Abstract

Approaches for patterning semiconductor or other wafers and dies are described. For example, a method of patterning features within a substrate involves forming a mask layer above a surface of a semiconductor or glass substrate. The method also involves laser ablating the mask layer to provide a pattern of openings through the mask layer. The method also involves plasma etching portions of the semiconductor or glass substrate through the pattern of openings to provide a plurality of trenches in the semiconductor or glass substrate. The plurality of trenches has a pattern corresponding to the pattern of openings and comprising a pattern of through-substrate-via openings or redistribution layer (RDL) openings. The method also involves, subsequent to the plasma etching, removing the mask layer.

First claim

What is claimed is:

1. A method of patterning features within a silicon substrate, the method comprising:
forming an insulating layer formed on the surface of the silicon substrate;
forming a mask layer on a surface of a silicon substrate;
laser ablating the mask layer and the insulating layer to provide a pattern of openings through the mask layer and in the insulating layer; and wherein the laser ablating comprises a picosecond laser using a single pulse ablation process;
plasma etching portions of the silicon substrate through the pattern of openings to provide a plurality of trenches extends through the entire thickness of the silicon substrate without dicing the silicon substrate, the plurality of trenches having a pattern corresponding to the pattern of openings and comprising a pattern of redistribution layer (RDL) openings;
and
subsequent to the plasma etching, removing the mask layer using a plasma ashing or wet cleaning process; wherein the laser ablating comprises laser ablating the mask layer but not the insulating layer, and wherein the plasma etching further comprises etching portions of the insulating layer through the openings to provide the pattern in the insulating layer and wherein the plasma etching is an ultra-high-density plasma source.

2. The method of claim 1 , wherein the pattern of the plurality of trenches is a pattern of through-silicon-via (TSV) openings.

3. The method of claim 1 , wherein each of the plurality of trenches extends through the entire thickness of the silicon substrate.

4. The method of claim 1 , wherein forming the mask layer comprises forming a layer of polyimide or a layer of polyvinyl alcohol (PVA).

5. A method of patterning features within a silicon substrate, the method comprising:
forming an insulating layer formed on the surface of the silicon substrate;
forming a mask layer on a surface of a silicon substrate, wherein forming the mask layer comprises forming a layer of polyimide or a layer of polyvinyl alcohol (PVA);
laser ablating the mask layer and the insulating layer to provide a pattern of openings through the mask layer and in the insulating layer, and wherein the laser ablating comprises a picosecond laser using a single pulse ablation process;
plasma etching portions of the silicon substrate through the pattern of openings to provide a plurality of trenches extends through the entire thickness of the silicon substrate without dicing the silicon substrate, the plurality of trenches having a pattern corresponding to the pattern of openings and comprising a pattern of through-substrate-via openings or redistribution layer (RDL) openings;
and
subsequent to the plasma etching, removing the mask layer using a plasma ashing or wet cleaning process;
wherein the laser ablating comprises laser ablating the mask layer but not the insulating layer, and wherein the plasma etching further comprises etching portions of the insulating layer through the openings to provide the pattern in the insulating layer and wherein the plasma etching is an ultra-high-density plasma source.

Assignees

• Applied Materials Inc

Inventors

• Lei Wei-Sheng
• Eaton Brad
• Kumar Ajay

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/072

  of bump connectors · CPC title