Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

Patent metadata

Field	Value
Publication number	US-9064936-B2
Application number	US-201313832333-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Dec 12, 2008
Publication date	Jun 23, 2015
Grant date	Jun 23, 2015

Abstract

A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.

First claim

What is claimed:

1. A semiconductor device, comprising:
a semiconductor die;
a conductive layer formed over the semiconductor die;
an encapsulant deposited around the semiconductor die;
a first insulating layer formed over a surface of the semiconductor die opposite the conductive layer; and
an interconnect structure formed through the encapsulant and first insulating layer outside a footprint of the semiconductor die.

2. The semiconductor device of claim 1 , further including a second insulating layer formed over the semiconductor die, wherein the second insulating layer includes an optically transparent or translucent material.

3. The semiconductor device of claim 1 , wherein the interconnect structure further includes:
an opening formed through the encapsulant over the conductive layer; and
a conductive material deposited in the opening electrically connected to the conductive layer.

4. The semiconductor device of claim 1 , further including a conductive via formed through the first insulating layer outside the footprint of the semiconductor die.

5. The semiconductor device of claim 1 , further including a plurality of stacked semiconductor devices electrically connected through the interconnect structure.

6. A semiconductor device, comprising:
a semiconductor die;
a conductive layer formed over the semiconductor die;
a first insulating layer formed over the semiconductor die; and
an interconnect structure formed outside a footprint of the semiconductor die through the first insulating layer and electrically connected to the conductive layer.

7. The semiconductor device of claim 6 , further including an encapsulant deposited over and around the semiconductor die and the interconnect structure.

8. The semiconductor device of claim 6 , further including a second insulating layer formed over the conductive layer.

9. The semiconductor device of claim 6 , wherein the interconnect structure includes a printed circuit board.

10. The semiconductor device of claim 8 , wherein the second insulating layer includes an optically transparent or translucent material.

11. The semiconductor device of claim 8 , wherein the semiconductor die further includes a sensor configured to receive an external stimulus passing through the second insulating layer.

12. The semiconductor device of claim 6 , further including a plurality of stacked semiconductor devices electrically connected through the interconnect structure.

Assignees

• Stats Chippac Ltd

Inventors

• Lin Yaojian
• Chen Kang
• Yoon Seung Wook

Classifications

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title