Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12356646-B2
Application number	US-202318360427-A
Country	US
Kind code	B2
Filing date	Jul 27, 2023
Priority date	Oct 30, 2018
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A method includes forming a gate structure across a channel region from a top view, the gate structure comprising a work function metal and a gate dielectric layer wrapping around the work function metal, the gate dielectric layer having a U-shaped cross-sectional profile; performing a first plasma etching process, by using a chlorine-containing reactant, on the gate structure; performing a second plasma etching process, by using a bromine-containing, reactant on the gate structure.

First claim

What is claimed is:

1. A method, comprising:
forming a gate structure across a channel region from a top view, the gate structure comprising a work function metal and a gate dielectric layer wrapping around the work function metal, the gate dielectric layer having a U-shaped cross-sectional profile;
performing a first plasma etching process, by using a first chlorine-containing reactant, on the gate structure; and
performing a second plasma etching process, by using a bromine-containing reactant, on the gate structure, wherein the bromine-containing reactant forms a metal bromide layer.

2. The method of claim 1 , wherein the first chlorine-containing reactant is free of bromine.

3. The method of claim 1 , wherein the first chlorine-containing reactant comprises boron trichloride.

4. The method of claim 1 , wherein the bromine-containing reactant comprises hydrogen bromide.

5. The method of claim 1 , wherein the second plasma etching process is performed after the first plasma etching process.

6. The method of claim 1 , wherein the second plasma etching process is performed by further using a reactant different than the bromine-containing reactant.

7. The method of claim 6 , wherein the reactant is a second chlorine-containing reactant.

8. The method of claim 1 , further comprising:
after performing the second plasma etching process, performing an ashing process on the gate structure.

9. The method of claim 1 , wherein the work function metal comprises tantalum nitride, titanium nitride, or a combination thereof.

10. The method of claim 1 , wherein the gate dielectric layer is made of metal oxide.

11. A method, comprising:
forming a channel region over a substrate;
forming an epitaxial source/drain structure adjacent to a sidewall of the channel region;
forming a gate structure over the channel region, the gate structure interfacing at least three surfaces of the channel region, wherein the gate structure comprises a work function metal and a gate dielectric layer around the work function metal, the gate dielectric layer has a U-shaped cross-sectional profile, and a top surface of the gate structure has a curved profile;
performing a chlorine-containing etching process on the work function metal; and
performing a bromine-containing etching process on the gate dielectric layer, wherein performing the bromine-containing etching process forms a metal bromide layer.

12. The method of claim 11 , wherein the metal bromide layer is formed over the work function metal.

13. The method of claim 12 , wherein the metal bromide layer has a thickness less than about 1 nm.

14. The method of claim 12 , wherein the metal bromide layer comprises titanium bromide, tantalum bromide, or a combination thereof.

15. The method of claim 12 , further comprising:
after performing the bromine-containing etching process, performing an ashing process on the metal bromide layer.

16. A method, comprising:
forming a channel region over a substrate;
forming an isolation dielectric disposed over the substrate and around a lower portion of the channel region;
forming a gate spacer over the isolation dielectric, wherein at least a portion of the gate spacer is over the channel region;
forming a gate structure extending along surfaces of a top portion of the channel region and a top surface of the isolation dielectric, wherein the gate structure comprises a work function metal and a gate dielectric layer around the work function metal, the gate dielectric layer has a U-shaped cross-sectional profile, the gate spacer extends along a sidewall of the gate structure, and a thickness of the gate spacer is greater than a thickness of the gate dielectric layer;
performing a chlorine-containing etching process on the gate structure; and
performing a bromine-containing etching process on the gate structure, wherein performing the bromine-containing etching process forms a metal bromide layer.

17. The method of claim 16 , wherein the work function metal comprises tantalum nitride, titanium nitride, or a combination thereof.

18. The method of claim 16 , wherein the bromine-containing etching process is performed such that a metal bromide forms over the work function metal.

19. The method of claim 18 , wherein the metal bromide has a top surface and a bottom surface more curved than the top surface.

20. The method of claim 18 , wherein the metal bromide has a topmost position lower than a topmost position of the gate dielectric layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Jung-Hao
• Lin Li-Te

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/267

  using plasmas · CPC title

• H10P50/285

  of materials not containing Si, e.g. PZT or Al2O3 · CPC title

• H10P70/27

  during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers · CPC title

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title