Self-Aligned Metal Gate Etch Back Process And Device

Patent metadata

Field	Value
Publication number	US-2017222005-A1
Application number	US-201615287509-A
Country	US
Kind code	A1
Filing date	Oct 6, 2016
Priority date	Jan 29, 2016
Publication date	Aug 3, 2017
Grant date	—

Abstract

A method of forming a semiconductor device includes receiving a device having a substrate and a first dielectric layer surrounding a gate trench. The method further includes depositing a gate dielectric layer and a gate work function (WF) layer in the gate trench, and forming a hard mask (HM) layer in a space surrounded by the gate WF layer. The method further includes recessing the gate WF layer such that a top surface of the gate WF layer in the gate trench is below a top surface of the first dielectric layer. After the recessing of the gate WF layer, the method further includes removing the HM layer in the gate trench. After the removing of the HM layer, the method further includes depositing a metal layer in the gate trench.

First claim

What is claimed is:

1 . A method of forming a semiconductor device, comprising:
receiving a device having a substrate and a first dielectric layer over the substrate, the first dielectric layer surrounding a gate trench; depositing a gate dielectric layer in the gate trench; depositing a gate work function (WF) layer in the gate trench and over the gate dielectric layer; forming a hard mask (HM) layer in a space that is in the gate trench and surrounded by the gate WF layer; recessing the gate WF layer such that a top surface of the gate WF layer in the gate trench is below a top surface of the first dielectric layer; after the recessing of the gate WF layer, removing the HM layer in the gate trench; and after the removing of the HM layer, depositing a metal layer in the gate trench.

2 . The method of claim 1 , further comprising, before the depositing of the metal layer:
recessing the gate dielectric layer such that a top surface of the gate dielectric layer in the gate trench is below the top surface of the first dielectric layer.

3 . The method of claim 1 , further comprising:
forming a gate contact over the metal layer and electrically connecting to the metal layer.

4 . The method of claim 1 , wherein the recessing of the gate WF layer includes a selective etching process that is tuned to etch the gate WF layer while the first dielectric layer and the HM layer remain substantially unchanged.

5 . The method of claim 1 , wherein the recessing of the gate WF layer also recesses the gate dielectric layer such that a top surface of the gate dielectric layer in the gate trench is below the top surface of the first dielectric layer.

6 . The method of claim 1 , wherein the removing of the HM layer includes a selective etching process that is tuned to etch the HM layer while the first dielectric layer, the gate dielectric layer, and the gate WF layer remain substantially unchanged.

7 . The method of claim 1 , further comprising, before the forming of the HM layer:
etching the gate WF layer to provide the space.

8 . The method of claim 1 , wherein the forming of the HM layer includes:
depositing a HM material over the substrate and filling the space; and etching back the HM material.

9 . The method of claim 8 , wherein the etching back of the HM material includes a selective etching process that is tuned to etch the HM material while the first dielectric layer, the gate dielectric layer, and the gate WF layer remain substantially unchanged.

10 . The method of claim 8 , wherein the etching back of the HM material includes a chemical mechanical planarization (CMP) process.

11 . The method of claim 1 , wherein the device further includes a gate spacer as the sidewalls of the gate trench.

12 . A method of forming a semiconductor device, comprising:
receiving a device having a substrate, a gate spacer over the substrate and providing a gate trench, and a first dielectric layer over the substrate and surrounding the gate spacer; depositing a gate dielectric layer on a bottom and sidewalls of the gate trench; depositing a gate work function (WF) layer in the gate trench and over the gate dielectric layer; forming a hard mask (HM) layer over the substrate and filling a space surrounded by the gate WF layer; etching the HM layer such that a top surface of the HM layer in the gate trench is below a top surface of the first dielectric layer; etching the gate WF layer such that a top surface of the gate WF layer in the gate trench is below the top surface of the first dielectric layer; etching the gate dielectric layer such that a top surface of the gate dielectric layer in the gate trench is below the top surface of the first dielectric layer; removing the HM layer in the gate trench, thereby providing a first space surrounded by the gate WF layer and a second space between the respective top surfaces of the gate WF layer and the gate dielectric layer and the top surface of the first dielectric layer; and filling a metal layer in the first and second spaces.

13 . The method of claim 12 , wherein each of the etching of the HM layer and the removing of the HM layer includes a selective etching process that is tuned to etch the HM layer while the gate spacer, the first dielectric layer, the gate dielectric layer, and the gate WF layer remain substantially unchanged.

14 . The method of claim 12 , wherein the etching of the gate WF layer includes a selective etching process that is tuned to etch the gate WF layer while the gate spacer, the first dielectric layer, and the HM layer remain substantially unchanged.

15 . The method of claim 12 , wherein the etching of the gate WF layer and the etching of the gate dielectric layer are performed in one fabrication step.

16 . A semiconductor device, comprising:
a substrate; a first dielectric layer over the substrate and surrounding a gate trench; a gate dielectric layer over a bottom and sidewalls of the gate trench; a gate work function (WF) layer over the gate dielectric layer in the gate trench, wherein a top surface of the gate WF layer is lower than a top surface of the first dielectric layer; and a metal layer filling a first space and a second space in the gate trench, wherein the first space is surrounded by the gate WF layer and the second space is between the top surface of the gate WF layer and the top surface of the first dielectric layer.

17 . The semiconductor device of claim 16 , further comprising a gate spacer as the sidewalls of the gate trench.

18 . The semiconductor device of claim 16 , wherein a top surface of the gate dielectric layer is lower than the top surface of the first dielectric layer, and the metal layer fills a third space between the top surface of the gate dielectric layer and the top surface of the first dielectric layer.

19 . The semiconductor device of claim 16 , wherein the gate dielectric layer comprises a high-k dielectric material and the metal layer comprises one of: aluminum (Al), tungsten (W), copper (Cu), and cobalt (Co).

20 . The semiconductor device of claim 16 , further comprising:
a gate contact directly contacting the metal layer, wherein the gate contact does not directly contact the gate WF layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Chih-Han
• Chang Che-Cheng
• Tseng Horng-Huei

Classifications

• H10D64/01324

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/01316

  the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al · CPC title

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H01L29/42364 Primary

  Electricity · mapped topic