Metal gate and manufuacturing process thereof

Patent metadata

Field	Value
Publication number	US-9577067-B2
Application number	US-201414463953-A
Country	US
Kind code	B2
Filing date	Aug 20, 2014
Priority date	Aug 20, 2014
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

Some embodiments of the present disclosure provide a semiconductor device including a semiconductive substrate, a metal gate including a metallic layer proximal to the semiconductive substrate. A dielectric layer surrounds the metal gate. The dielectric layer includes a first surface facing the semiconductive substrate and a second surface opposite to the first surface. A sidewall spacer surrounds the metallic layer with a greater longitudinal height. The sidewall spacer is disposed between the metallic layer and the dielectric layer. An etch stop layer over the metal gate comprises a surface substantially coplanar with the second surface of the dielectric layer. The etch stop layer has a higher resistance to etchant than the dielectric layer. A portion of the etch stop layer is over the sidewall spacer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductive substrate;
a metal gate comprising a metallic layer proximal to the semiconductive substrate;
a dielectric layer surrounding the metal gate and including a first surface facing the semiconductive substrate and a second surface opposite to the first surface;
a sidewall spacer surrounding the metallic layer with a greater longitudinal height and disposed between the metallic layer and the dielectric layer, wherein the sidewall spacer includes a bottom landing on the semiconductive substrate and a top opposite to the bottom;
an etch stop layer over the metal gate and comprising a surface substantially coplanar with the second surface of the dielectric layer, wherein the etch stop layer has a higher resistance to etchant than the dielectric layer, a first portion of the etch stop layer is disposed alongside a sidewall of the sidewall spacer, a second portion of the etch stop layer is over the sidewall spacer and the first portion, and the first portion is narrower than the second portion; and
a second dielectric layer laterally lying on the dielectric layer, wherein the second portion of the etch stop layer is between the sidewall spacer and the second dielectric layer,
wherein a top of the metal gate is recessed from the top of the sidewall spacer.

2. The semiconductor device of claim 1 , wherein a height of the sidewall spacer is measured from the bottom to the top.

3. The semiconductor device of claim 1 , wherein the etch stop layer covers the top of the sidewall spacer.

4. The semiconductor device of claim 1 , wherein the top of the sidewall spacer is recessed from the second surface of the dielectric layer with a predetermined distance.

5. The semiconductor device of claim 4 , wherein the predetermined distance is between about 10 Å and about 700 Å.

6. The semiconductor device of claim 1 , wherein the etch stop layer includes silicon nitride.

7. The semiconductor device of claim 1 , further comprising a conductive plug in the dielectric layer, wherein the conductive plug contacts a raised doped region in the semiconductive substrate.

8. The semiconductor device of claim 1 , wherein the semiconductive substrate further comprising a doped region with a different conductive type than the semiconductive substrate.

9. The semiconductor device of claim 8 , wherein the doped region is an epitaxial layer.

10. The semiconductor device of claim 1 , wherein the metal gate further comprises a work function layer.

11. The semiconductor device of claim 1 , further comprising contact etch stop layer.

12. A semiconductor device, comprising:
a semiconductive substrate;
a dielectric layer laterally placed over the semiconductive substrate, wherein the dielectric layer includes a first surface facing the semiconductive substrate and a second surface opposite to the first surface;
a metal gate structure surrounded by the dielectric layer, wherein the metal gate structure comprises a gate length, and a top of the metal gate structure is recessed from the second surface of the dielectric layer;
a sidewall spacer between the metal gate structure and the dielectric layer, wherein a top of the metal gate structure is recessed from a top of the sidewall spacer;
a contact etch stop layer between the dielectric layer and the metal gate structure; and
a nitrogen containing layer covering the metal gate structure, wherein the nitrogen containing layer comprises a lateral width greater than the gate length of the metal gate structure, and the nitrogen containing layer covers a top of the contact etch stop layer.

13. The semiconductor device of claim 12 , wherein the sidewall spacer is covered by the nitrogen containing layer.

14. A method for fabricating semiconductor device, comprising:
forming a semiconductive substrate;
forming a replacement gate in proximity to the semiconductive substrate;
forming a sidewall spacer surrounding the replacement gate;
forming a contact etch stop layer surrounding the replacement gate;
forming a dielectric layer surrounding the contact etch stop layer;
planarizing the dielectric layer;
recessing the contact etch stop layer and the replacement gate;
forming a metal gate to replace the replacement gate, wherein forming the metal gate comprises:
forming at least one metal layer over the semiconductive substrate, the contact etch stop layer and the dielectric layer; and
etching the at least one metal layer to form the metal gate; and

forming an etch stop layer over the metal gate, the contact etch stop layer and the sidewall spacer, wherein the etch stop layer is in contact with the sidewall spacer.

15. The method of claim 14 , wherein the planarizing comprises forming an upper surface of the dielectric layer coplanar with a top surface of the contact etch stop layer.

16. The method of claim 14 , wherein the recessing comprises lowering the contact etch stop layer by a predetermined distance.

17. The method of claim 16 , wherein the predetermined distance is between about 10 Å and about 700 Å.

18. The method of claim 14 , further comprising depositing a nitrogen containing layer over the metal gate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ho Wei-Shuo
• Chen chang-yin
• Chang Chai-Wei
• Chiang Tsung-Yu

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H01L29/66553

  Electricity · mapped topic

• H01L29/513

  Electricity · mapped topic

• H01L29/518

  Electricity · mapped topic

• H01L29/66545 Primary

  Electricity · mapped topic