System and method for calibrating weighting errors in split capacitance successive approximation analog-to-digital converters

Patent metadata

Field	Value
Publication number	US-12355461-B2
Application number	US-202318472717-A
Country	US
Kind code	B2
Filing date	Sep 22, 2023
Priority date	Aug 2, 2023
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

The present disclosure relates to the field of microelectronics and solid-state electronics, and in particular to a calibration system and method for weighting errors brought about by parasitic capacitance in split capacitor-based successive approximation analog-to-digital converters. The method uses an MSB array that does not add additional capacitors, only a switch SM to reduce the comparator design difficulty. Meanwhile, an LSB array may add a calibration DAC array CA including a binary array of P-bit unit capacitors, a calibration structure Cfraq, and a ground switch Sk. The calibration structure Cfraq includes four unit capacitors and two switches S1 and S2. By controlling the switches S1 and S2 different capacitance values can be generated to reduce the chip area consumption. This structure can reduce the error to LSB/4 and the weighting error of the ADC, and increases the effective number of bits of the ADC without excessively increasing comparator gain.

First claim

What is claimed:

1. A system for calibrating weighting errors in an analog-to-digital converter (ADC), comprising:
a comparator, a P-terminal array, a N-terminal array and a control logic unit;
wherein the comparator has a positive input terminal and a negative input terminal switchably connectable to a common mode reference voltage;
the positive input of the comparator is connected to the P-terminal array;
the P-terminal array comprises a least significant bit (LSB) array having L bits, a bridge capacitor C BR , and a most significant bit (MSB) array having M bits;
the negative input of the comparator is connected to the N-terminal array;
the MSB array contains 2 M −1 unit capacitances, wherein a first capacitor corresponding to the unit capacitances has a first plate connected directly to the comparator, each remaining capacitor corresponding to the unit capacitances has a first plate switchably connected to the comparator, and each of the capacitors corresponding to the unit capacitances has a lower plate with a common connection that is switchably connected to a positive reference voltage, a negative reference voltage, or a differential positive input voltage;
the LSB array contains 2 L unit capacitors, wherein each of the unit capacitors has an upper plate connected to the comparator and a lower plate switchably connected to the positive reference voltage, the negative reference voltage, or the differential positive input voltage;
the bridge capacitor is between a common connection point of the upper plates of the LSB array unit capacitors and an upper plate common connection point of the capacitors corresponding to the unit capacitances in the MSB array;
the system further comprises a calibration digital-to-analog converter (DAC) array connected to the upper plates of the LSB array unit capacitors, wherein the calibration DAC array comprises a binary array of P-bit unit capacitors, a calibration structure, and a ground switch group, and the calibration structure includes (i) a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor connected in series and (ii) a first switch and a second switch configured to generate a plurality of capacitance values from the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor; and
the control logic unit outputs the positive reference voltage, the negative reference voltage, or the differential positive input voltage.

2. The system of claim 1 , having an effective number of ADC bits equal to M+L.

3. The system of claim 1 , wherein the ADC is a split capacitance successive approximation analog-to-digital converter.

4. The system of claim 1 , wherein the N-terminal array is a mirror image of the P-terminal array.

5. The system of claim 1 , wherein the capacitors corresponding to the unit capacitances comprise a first plurality of capacitors having a first unit capacitance, a second unit capacitance, a third unit capacitance and a fourth unit capacitance.

6. The system of claim 5 , wherein the second unit capacitance is twice the first unit capacitance, the third unit capacitance is four times the first unit capacitance, and the fourth unit capacitance is eight times the first unit capacitance.

7. The system of claim 1 , wherein the LSB array contains a second plurality of capacitors having a fifth unit capacitance, a sixth unit capacitance, a seventh unit capacitance and an eighth unit capacitance.

8. The system of claim 7 , wherein the second plurality of capacitors comprises two capacitors having the fifth unit capacitance, the sixth unit capacitance is twice the fifth unit capacitance, the seventh unit capacitance is four times the fifth unit capacitance, and the eighth unit capacitance is eight times the fifth unit capacitance.

9. The system of claim 1 , wherein the binary array of P-bit unit capacitors comprises a third plurality of capacitors having a ninth unit capacitance, a tenth unit capacitance, an eleventh unit capacitance and a twelfth unit capacitance.

10. The system of claim 9 , wherein the tenth unit capacitance is twice the ninth unit capacitance, the eleventh unit capacitance is four times the ninth unit capacitance, and the twelfth unit capacitance is eight times the ninth unit capacitance.

11. The system of claim 9 , wherein each of the third plurality of capacitors has a lower plate switchably connectable to a ground potential.

12. The system of claim 1 , wherein the calibration structure comprises a first unit capacitor, a second unit capacitor, a third unit capacitor, and a fourth unit capacitor connected in series and two switches.

13. The system of claim 12 , wherein each of the first through fourth unit capacitors has a first plate and a second plate, the first plate of the first unit capacitor is connected to the second plate of the second unit capacitor, the first plate of the second unit capacitor is connected to the second plate of the third unit capacitor, and the first plate of the third unit capacitor connects to the second plate of the fourth unit capacitor.

14. The system of claim 12 , wherein the two switches are connected to the second plate of the first unit capacitor, one of the two switches is connected between the second unit capacitor and the third unit capacitor, and the other of the two switches is connected between the third unit capacitor and the fourth unit capacitor.

15. The system of claim 12 , wherein the first plate of the fourth unit capacitor and a first plate of each capacitor in the binary array of P-bit unit capacitors are connected in common and to the LSB array.

16. The system of claim 1 , wherein the calibration DAC array further comprises a plurality of control switches configured to adjust an equivalent capacitance value of the calibration DAC array and/or the calibration structure.

17. A method of calibrating weighting errors due to parasitic capacitance in an analog-to-digital converter, comprising:
disconnecting P-terminal and N-terminal switches;
connecting a first plate of a most significant bit (MSB) array to a common mode voltage, connecting the second plate of a unit capacitor to a first reference voltage, and connecting a second plate of a plurality of least significant bit (LSB) array capacitors to a second reference voltage;
disconnecting a common mode voltage switch from the first plate of the MSB array;
switching a second plate of the unit capacitor in the MSB array to the second reference voltage, and switching a second plate of the LSB array capacitors to the first reference voltage;
stabilizing a voltage at ends of a comparator, such that a voltage difference between the ends of the comparator is a voltage difference caused by the weighting error; and
repeating (i) connecting the first plate of the MSB array to the common mode voltage, connecting the second plate of the unit capacitor to the first reference voltage, and connecting the second plate of the plurality of LSB array capacitors to the second reference voltage, (ii) switching the second plate of the unit capacitor in the MSB array to the second reference voltage and switching the second plate of the LSB array capacitors to the first reference voltage, and (iii) stabilizing the voltage at the ends of the comparator to converge the digital value and/or the output of the calibration capacitor array to a fixed value, thereby completing the calibration.

18. The method of claim 17 , further comprising inputting a comparator result to successive-approximation-register (SAR) control logic, and controlling a plurality of switches in

Assignees

• Univ Electronic Science And Tech Of China
• Univ Electronic Sci & Tech China

Inventors

• Fan Hua
• Liu Yilin
• Zhang Wei
• Luo Jing
• Zhao Panfeng
• Feng Quanyuan

Classifications

• H03M1/462 Primary

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/406

  using current mode circuits, i.e. circuits in which the information is represented by current values rather than by voltage values · CPC title

• H03M1/1061

  using digitally programmable trimming circuits · CPC title

• H03M1/804

  with charge redistribution · CPC title

• H03M1/466

  using switched capacitors · CPC title