Threshold detection with digital correction in analog to digital converters

Patent metadata

Field	Value
Publication number	US-9680492-B1
Application number	US-201615246369-A
Country	US
Kind code	B1
Filing date	Aug 24, 2016
Priority date	Aug 24, 2016
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

An analog to digital converter (ADC) includes a comparator and a plurality of capacitor pairs coupled between first and second inputs the comparator, where each one of the capacitor pairs corresponds to one of a plurality of cycles used by the ADC to generate a digital value representing a sampled analog voltage. The ADC also includes a voltage detection circuit and a state machine that is configured to, upon determining during a first cycle that the sampled voltage across the first and second inputs satisfies a threshold, maintaining a first pair of the plurality of capacitor pairs in a default state such that the sampled analog voltage is unchanged. Otherwise, the state machine is configured to switch the first pair of the plurality of capacitor pairs to change the sampled analog voltage.

First claim

What is claimed is:

1. An analog to digital converter (ADC), comprising:
a comparator;
a plurality of capacitor pairs coupled between a first input and a second input of the comparator, wherein each one of the capacitor pairs corresponds to one of a plurality of cycles used by the ADC to generate a digital value representing a sampled analog voltage;
a voltage detection circuit coupled between the first and second inputs; and
a state machine configured to:
upon determining during a first cycle of the plurality of cycles that the voltage detection circuit indicates the sampled analog voltage across the first and second inputs satisfies a threshold, maintaining a first pair of the plurality of capacitor pairs corresponding to the first cycle in a reset state such that the sampled analog voltage is unchanged; and
upon determining during the first cycle that the voltage detection circuit indicates the sampled analog voltage across the first and second inputs does not satisfy the threshold, switching the first pair of the plurality of capacitor pairs to change the sampled analog voltage.

2. The ADC of claim 1 , wherein the state machine is configured to:
upon determining during a second cycle of the plurality of cycles that the voltage detection circuit indicates the sampled analog voltage across the first and second inputs satisfies the threshold, maintaining a second pair of the plurality of capacitor pairs corresponding to the second cycle in the reset state such that the sampled analog voltage is unchanged; and
upon determining during the second cycle that the voltage detection circuit indicates the sampled voltage across the first and second inputs does not satisfy the threshold, switch the second pair of the plurality of capacitor pairs to change the sampled analog voltage.

3. The ADC of claim 1 , wherein a value of the two capacitors in each of the capacitors pairs is the same, and wherein the values for each of the capacitor pairs is different relative to the values of the other capacitor pairs.

4. The ADC of claim 1 , wherein switching the first pair of the plurality of capacitor pairs performs an analog operation on the sampled analog voltage, and wherein maintaining the first pair of the plurality of capacitors in the reset state skips the analog operation.

5. The ADC of claim 4 , wherein upon determining during the first cycle that the voltage detection circuit indicates the sampled analog voltage across the first and second inputs satisfies the threshold, the state machine is configured to:
store an indication that digital correction of the digital value is needed.

6. The ADC of claim 5 , wherein the state machine is configured to:
upon determining all of the plurality of cycles have been performed, perform a digital operation on the digital value to compensate for skipping the analog operation during the first cycle.

7. The ADC of claim 1 , wherein the state machine is configured to:
evaluate an output of the voltage detection circuit during only a subset of the plurality of cycles to determine whether to maintain one or more of the plurality of capacitor pairs in the reset state, wherein the output of the voltage detection circuit is ignored during a remainder of the plurality of cycles.

8. The ADC of claim 1 , wherein the ADC is a successive approximation register ADC.

9. An integrated circuit, comprising:
a comparator;
a plurality of capacitor pairs coupled between a first input and a second input of the comparator, wherein each one of the capacitor pairs corresponds to one of a plurality of cycles used to generate a digital value representing a sampled analog voltage;
a voltage detection circuit coupled between the first and second inputs; and
a state machine configured to:
upon determining during a first cycle of the plurality of cycles that the voltage detection circuit indicates the sampled analog voltage across the first and second inputs satisfies a threshold, maintaining a first pair of the plurality of capacitor pairs corresponding to the first cycle in a reset state such that the sampled analog voltage is unchanged; and
upon determining during the first cycle that the voltage detection circuit indicates the sampled analog voltage across the first and second inputs does not satisfy the threshold, switch the first pair of the plurality of capacitor pairs to change the sampled analog voltage.

10. The integrated circuit of claim 9 , wherein the state machine is configured to:
upon determining during a second cycle of the plurality of cycles that the voltage detection circuit indicates the sampled analog voltage across the first and second inputs satisfies the threshold, maintaining a second pair of the plurality of capacitor pairs corresponding to the second cycle in the reset state such that the sampled analog voltage is unchanged; and
upon determining during the second cycle that the voltage detection circuit indicates the sampled voltage across the first and second inputs does not satisfy the threshold, switching the second pair of the plurality of capacitor pairs to change the sampled analog voltage.

11. The integrated circuit of claim 9 , wherein a value of the two capacitors in each of the capacitors pairs is the same, and wherein the values for each of the capacitor pairs is different relative to the values of the other capacitor pairs.

12. The integrated circuit of claim 9 , wherein switching the first pair of the plurality of capacitor pairs performs an analog operation on the sampled analog voltage, and wherein maintaining the first pair of the plurality of capacitors in the reset state skips the analog operation.

13. The integrated circuit of claim 12 , wherein upon determining during the first cycle that the voltage detection circuit indicates the sampled analog voltage across the first and second inputs satisfies the threshold, the state machine is configured to:
store an indication that digital correction of the digital value is needed.

14. The integrated circuit of claim 13 , wherein the state machine is configured to:
upon determining all of the plurality of cycles have been performed, perform a digital operation on the digital value to compensate for skipping the analog operation during the first cycle.

15. The integrated circuit of claim 9 , wherein the state machine is configured to:
evaluate an output of the voltage detection circuit during only a subset of the plurality of cycles to determine whether to maintain one or more of the plurality of capacitor pairs in the reset state, wherein the output of the voltage detection circuit is ignored during a remainder of the plurality of cycles.

16. The integrated circuit of claim 9 , wherein the comparator, the plurality of capacitor pairs, the voltage detection circuit and the state machine form a successive approximation register ADC.

17. A method, comprising:
receiving a first sampled analog voltage at a first input and a second input of a comparator in an ADC, wherein a plurality of capacitor pairs are coupled between the first and second inputs of the comparator, and wherein each one of the capacitor pairs corresponds to one of a first plurality of cycles used by the ADC to generate a digital value representing the first sampled analog voltage;
upon determining during a first cycle of the first plurality of cycles that the first sampled analog voltage satisfies a threshold, maintaining a first pair of the plurality of capacitor pairs corresponding to the first cycle in a reset state such that the first sampled analog voltage is unchanged;
receiving a second sampled

Assignees

• Xilinx Inc

Inventors

• Farley Brendan
• Erdmann Christophe

Classifications

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/1245 Primary

  Details of sampling arrangements or methods · CPC title

• H03M1/0863 Primary

  of switching transients, e.g. glitches · CPC title

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title