Charge-redistribution successive approximation ADC and control method thereof

Patent metadata

Field	Value
Publication number	US-9859912-B2
Application number	US-201615381830-A
Country	US
Kind code	B2
Filing date	Dec 16, 2016
Priority date	Jan 19, 2016
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A charge-redistribution successive approximation ADC includes: a comparator, generating a comparison result; a register, storing a digital output code, determining a bit value of the digital output code according to the comparison value; a control unit, generating a control signal according to the digital output code; a plurality of first capacitors, each including a first end and a second end, the first end coupled to a first input end of the comparator; at least one second capacitor, including a third end and a fourth end, the third end coupled to the first input end of the comparator. Before the voltages of the second end of each first capacitor and the fourth end of the second capacitor are switched, the second end is coupled to a first voltage and the fourth end is coupled to a second voltage different from the first voltage.

First claim

What is claimed is:

1. A charge-redistribution successive approximation analog-to-digital converter (ADC), applied to a single-ended signal, comprising:
a comparator, receiving the single-ended signal, and generating a comparison result;
a register, coupled to the comparator, storing a digital output code, determining bit values of the digital output code according to the comparison result;
a control circuit, coupled to the register, generating a control signal according to the digital output code;
a plurality of first capacitors, each of the first capacitors comprising a first end and a second end, the first end coupled to a first input end of the comparator;
at least one second capacitor, comprising a third end and a fourth end, the third end coupled to the first input end of the comparator; and
at least one third capacitor, coupled to a second input end of the comparator;
wherein, when the control signal controls the second end of one of the first capacitors to switch from a first voltage to a second voltage, the fourth end of the second capacitor is kept at the second voltage; when the control signal controls the fourth end of the second capacitor to switch from the second voltage to the first voltage, the second end of the first capacitor is kept at the first voltage;
wherein, a total of the numbers of the second capacitor(s) and the third capacitor(s) is equal to the number of the first capacitors.

2. The charge-redistribution successive approximation ADC according to claim 1 , wherein the second capacitor and one of the first capacitors have a substantially same capacitance value.

3. The charge-redistribution successive approximation ADC according to claim 1 , wherein before the voltages of the first capacitors and the second capacitor are switched, the second end of each of the first capacitors is coupled to the first voltage and the fourth end of the second capacitor is coupled to the second voltage.

4. The charge-redistribution successive approximation ADC according to claim 1 ,
wherein, the second capacitor and one of the first capacitors have substantially a same capacitance value, and the third capacitor and another of the first capacitors have substantially a same capacitance value.

5. The charge-redistribution successive approximation ADC according to claim 1 , wherein the second capacitor and the largest of the first capacitor have substantially a same capacitance value.

6. The charge-redistribution successive approximation ADC according to claim 1 , wherein the first input end of the comparator receives a data signal component of the single-ended signal, and a second input end of the comparator receives a common mode signal component of the single-ended signal.

7. A control method for a charge-redistribution successive approximation analog-to-digital converter (ADC), applied to a successive approximation ADC comprising a comparator, the control method comprising:
providing a plurality of first capacitors;
coupling a first end of each of the first capacitors to a first input end of the comparator, and coupling a second end of each of the first capacitors to a first voltage;
providing at least one second capacitor;
coupling a third end of the second capacitor to the first input end of the comparator, and coupling a fourth end of the second capacitor to a second voltage;
providing at least one third capacitor;
coupling a fifth end of the third capacitor to a second input end of the comparator, and coupling a sixth end of the third capacitor to the first voltage; and
controlling the second end of a target capacitor among the first capacitors to switch from the first voltage to the second voltage according to a comparison result of the comparator, or controlling the fourth end of the second capacitor to switch from the second voltage to the first voltage according to the comparison result;
wherein, a total of the numbers of the second capacitor(s) and the third capacitor(s) is equal to the number of the first capacitors.

8. The control method according to claim 7 , wherein the target capacitor and the second capacitor have substantially a same capacitance value.

9. The control method according to claim 8 , wherein the target capacitor is one with a largest capacitance value among the first capacitors.

10. The control method according to claim 7 ,
wherein, the second capacitor and the target capacitor have substantially a same capacitance value, and the third capacitor and another of the first capacitors have substantially a same capacitance value.

11. The control method according to claim 7 , further comprising:
inputting a data signal component of a single-ended signal to the first input end of the comparator; and
inputting a common mode signal component of the single-ended signal to a second input end of the comparator.

12. A charge-redistribution successive approximation analog-to-digital converter (ADC), comprising:
a comparator, generating a comparison result;
a register, coupled to the comparator, storing a digital output code, determining bit values of the digital output code according to the comparison result;
a control circuit, coupled to the register, generating a control signal according to the digital output code;
a plurality of first capacitors, each of the first capacitors comprising a first end and a second end, the first end coupled to a first input end of the comparator;
at least one second capacitor, comprising a third end and a fourth end, the third end coupled to the first input end of the comparator; and
at least one third capacitor, coupled to a second input end of the comparator;
wherein, before voltages of the second end of each of the first capacitors and the fourth end of the second capacitor are switched, the second end is coupled to a first voltage and the fourth end is coupled to a second voltage different from the first voltage;
wherein, a total of the numbers of the second capacitor(s) and the third capacitor(s) is equal to the number of the first capacitors.

13. The charge-redistribution successive approximation ADC according to claim 12 , wherein the second capacitor and one of the first capacitors have substantially a same capacitance value.

14. The charge-redistribution successive approximation ADC according to claim 12 ,
wherein, the second capacitor and one of the first capacitors have substantially a same capacitance value, and one of the third capacitor(s) and another of the first capacitors have substantially a same capacitance value.

15. The charge-redistribution successive approximation ADC according to claim 12 , wherein the second capacitor and the largest of the first capacitors have substantially a same capacitance value.

16. The charge-redistribution successive approximation ADC according to claim 12 , wherein the first input end of the comparator receives a data signal component of a single-ended signal, and a second input end of the comparator receives a common mode signal component of the single-ended signal.

Assignees

• Realtek Semiconductor Corp

Inventors

• Chung Kuo-Sheng
• Huang Shih-Hsiung

Classifications

• H03M1/466 Primary

  using switched capacitors · CPC title

• H03M1/1295 Primary

  Clamping, i.e. adjusting the DC level of the input signal to a predetermined value · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title