Method of fabricating a semiconductor package

Patent metadata

Field	Value
Publication number	US-12334445-B2
Application number	US-202318367039-A
Country	US
Kind code	B2
Filing date	Sep 12, 2023
Priority date	Aug 7, 2020
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

A semiconductor package and associated methods, the package including a substrate; first and second semiconductor chips on the substrate; and external terminals below the substrate, wherein the substrate includes a core portion; first and second buildup portions on top and bottom surfaces of the core portion, the first and second buildup portions including a dielectric pattern and a line pattern; and an interposer chip in an embedding region in the core portion and electrically connected to the first and second buildup portions, the interposer chip includes a base layer; a redistribution layer on the base layer; and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed at a surface of the base layer, the redistribution layer is connected to a line pattern of the first buildup portion, and the via is connected to a line pattern of the second buildup portion.

First claim

What is claimed is:

1. A method of fabricating a semiconductor package, the method comprising:
forming an interposer chip that includes a base layer, a redistribution layer on a first surface of the base layer, and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed on a second surface of the base layer;
providing the interposer chip into a core portion that includes a conductive element and an upper core pad disposed on and contacting an upper surface of the conductive element;
forming a first buildup portion on a top surface of the core portion and the first surface of the base layer, the first buildup portion being connected to the conductive element and the redistribution layer;
forming a second buildup portion on a bottom surface of the core portion and the second surface of the base layer, the second buildup portion being connected to the conductive element and the via;
mounting a plurality of semiconductor chips on the first buildup portion; and
forming on the first buildup portion a molding layer that covers the plurality of semiconductor chips,
wherein the plurality of semiconductor chips are electrically connected to each other through the first buildup portion and the interposer chip,
wherein the redistribution layer includes a chip conductive patter embedded in a chip dielectric laver,
wherein a top surface of the chip conductive pattern is located at the same level as a level of a top surface of the upper core pad, and
wherein a line pattern of the first buildup portion directly contacts the top surface of the chip conductive pattern.

2. The method as claimed in claim 1 , wherein the forming the interposer chip includes:
forming a hole inwardly directed from the first surface of the base layer;
filling the hole with a conductive material to form the via;
forming on the first surface of the base layer the redistribution layer coupled to the via; and
allowing the second surface of the base layer to undergo a thinning process to expose the via.

3. The method as claimed in claim 2 , wherein a top surface of the via is located at a same level as a level of the first surface of the base layer.

4. The method as claimed in claim 1 , wherein the plurality of semiconductor chips are flip-chip mounted on the first buildup portion.

5. The method as claimed in claim 1 , wherein the providing the interposer chip into the core portion includes:
providing the core portion that has the conductive element including a plurality of core conductive patterns;
forming an opening that penetrates an inside of the core portion; and
providing the interposer chip into the opening.

6. The method as claimed in claim 5 , further comprising forming an insulating layer by providing a dielectric material into the opening and a gap between the core portion and the interposer chip, before forming the first buildup portion or the second buildup portion.

7. The method as claimed in claim 1 , wherein providing the interposer chip into the core portion includes:
placing the interposer chip on a carrier substrate;
forming the core portion by coating on the carrier substrate a dielectric material that surrounds the interposer chip; and
forming the conductive element including a core via that vertically penetrates the core portion.

8. The method as claimed in claim 1 ,
wherein a top surface of the chip dielectric layer of the redistribution layer of the interposer chip is located at a same level as a level of the top surface of the core portion, and
wherein the top surface of the chip dielectric layer of the redistribution layer of the interposer chip is in contact with the first buildup portion.

9. The method as claimed in claim 1 , wherein:
the first buildup portion includes a dielectric pattern and the line pattern.

10. A method of fabricating a semiconductor package, the method comprising:
forming an interposer chip that includes a base layer, a redistribution layer on a first surface of the base layer, and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed on a second surface of the base layer;
forming an embedding region in a core portion that includes a conductive element and an upper core pad disposed on and contacting an upper surface of the conductive element;
providing the interposer chip into the embedding region in the core portion;
forming a first buildup portion on a top surface of the core portion and a top surface of interposer chip, the first buildup portion being connected to the core portion and the redistribution layer;
forming a second buildup portion on a bottom surface of the core portion and the second surface of the base layer, the second buildup portion being connected to the core portion and the via;
mounting a plurality of semiconductor chips on the first buildup portion; and
forming on the first buildup portion a molding layer that covers the plurality of semiconductor chips,
wherein the redistribution layer includes a chip conductive pattern embedded in a chip dielectric layer,
wherein a top surface of the chip conductive pattern is located at the same level as a level of a top surface of the upper core pad,
wherein a line pattern of the first buildup portion directly contacts the top surface of the chip conductive pattern,
wherein a top surface of the via is located at a same level as a level of the first surface of the base layer, and
wherein a top surface of the redistribution layer of the interposer chip is located at a same level as a level of the top surface of the core portion, and the top surface of the redistribution layer of the interposer chip is in contact with the first buildup portion.

11. The method as claimed in claim 10 , wherein forming the interposer chip includes:
forming a hole inwardly directed from the first surface of the base layer;
filling the hole with a conductive material to form the via;
forming on the first surface of the base layer the redistribution layer coupled to the via; and
allowing the second surface of the base layer to undergo a thinning process to expose the via.

12. The method as claimed in claim 10 , wherein the plurality of semiconductor chips are flip-chip mounted on the first buildup portion.

13. The method as claimed in claim 10 , wherein the providing the interposer chip into the embedding region in the core portion includes:
providing the core portion that has a plurality of core conductive patterns;
forming the embedding region that has an open hole shape that vertically penetrates the core portion; and
providing the interposer chip into the embedding region.

14. The method as claimed in claim 13 , further comprising forming an insulating layer by providing a dielectric material into the embedding region and a gap between the core portion and the interposer chip, before forming the first buildup portion or the second buildup portion.

15. The method as claimed in claim 13 , wherein
the interposer chip is spaced apart from an inner wall of the embedding region.

16. The method as claimed in claim 10 , wherein providing the interposer chip into the embedding region in the core portion includes:
placing the interposer chip on a carrier substrate;
forming the core portion by coating on the carrier substrate a dielectric material that surrounds the interposer chip; and
forming a core via that vertically penetrates the core portion.

17. The method as claimed in claim 10 , wherein:
the first buildup portion includes a dielectric pattern and the line pattern.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Myungsam
• Ko Youngchan
• Jeong Taesung

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title