Fan-out semiconductor package

Patent metadata

Field	Value
Publication number	US-10748856-B2
Application number	US-201816103199-A
Country	US
Kind code	B2
Filing date	Aug 14, 2018
Priority date	Mar 13, 2018
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

A fan-out semiconductor package includes: a core member having a first through-hole and including a dummy metal layer; a first semiconductor chip disposed in the first through-hole and having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface; a first encapsulant covering at least portions of the core member and the first semiconductor chip and filling at least portions of the first through-hole; and a first connection member disposed on the core member and the first active surface of the first semiconductor chip and including a first redistribution layer electrically connected to the first connection pads, wherein the dummy metal layer is electrically insulated from signal patterns of the first redistribution layer.

First claim

What is claimed is:

1. A fan-out semiconductor package comprising:
a core member having a first through-hole;
a first semiconductor chip disposed in the first through-hole and having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface;
a first encapsulant covering a portion of the core member and a portion of the first semiconductor chip and filling a portion of the first through-hole;
a first connection member disposed on the core member and the first active surface of the first semiconductor chip and including a first redistribution layer electrically connected to the first connection pads; and
a dummy metal layer disposed on the core member and electrically insulated from the first redistribution layer, the dummy metal layer having a thickness greater than that of the first redistribution layer;
a second semiconductor chip having a second active surface having second connection pads disposed thereon and a second inactive surface opposing the second active surface, the second inactive surface being attached to a lower surface of the first connection member;
a second encapsulant disposed on the lower surface of the first connection member and covering a portion of the second semiconductor chip;
a second redistribution layer disposed on the second encapsulant and the second active surface of the second semiconductor chip;
second redistribution vias penetrating through a portion of the second encapsulant and electrically connecting the second connection pads and the second redistribution layer to each other; and
third redistribution vias penetrating through the second encapsulant, penetrating through a portion of the first connection member and electrically connecting the first redistribution layer and the second redistribution layer to each other,
wherein the core member includes a wiring layer electrically connected to the first redistribution layer,
wherein the dummy metal layer has a thickness greater than that of the wiring layer, and
wherein each of the third redistribution vias has a height greater than that of each of the second redistribution vias.

2. The fan-out semiconductor package of claim 1 , wherein the wiring layer has a thickness greater than that of the first redistribution layer.

3. The fan-out semiconductor package of claim 1 , wherein the dummy metal layer is disposed at an uppermost portion of the core member.

4. The fan-out semiconductor package of claim 3 , wherein the dummy metal layer includes one or more dummy pattern formed along an edge of the core member.

5. The fan-out semiconductor package of claim 4 , wherein the dummy pattern is continuously formed without being disconnected, to correspond to the edge of the core member.

6. The fan-out semiconductor package of claim 5 , wherein the number of dummy patterns is plural,
a wiring pattern is disposed between the plurality of dummy patterns, and
each of the plurality of dummy patterns has a thickness greater than that of the wiring pattern.

7. The fan-out semiconductor package of claim 1 , wherein when the second and third redistribution vias are cut on the same level by a surface parallel with the second active surface, a length of a long side of a cut surface of the third redistribution via is greater than that of a long side of a cut surface of the second redistribution via on any level.

8. The fan-out semiconductor package of claim 1 , wherein the second inactive surface of the second semiconductor chip is attached to the lower surface of the first connection member through a die attach film (DAF).

9. The fan-out semiconductor package of claim 1 , further comprising a third semiconductor chip having a third active surface having third connection pads disposed thereon and a third inactive surface opposing the third active surface,
wherein the core member further has a second through-hole spaced apart from the first through-hole,
the third semiconductor chip is disposed in the second through-hole side by side with the first semiconductor chip,
the first encapsulant covers at least a portion of the third semiconductor chip and fills at least a portion of the second through-hole, and
the first, connection member is also disposed on the third active surface of the third semiconductor chip, and the first redistribution layer is also electrically connected to the third connection pads.

10. The fan-out semiconductor package of claim 9 , further comprising a fourth semiconductor chip having a fourth active surface having fourth connection pads disposed thereon and a fourth inactive surface opposing the fourth active surface,
wherein the fourth semiconductor chip is disposed side by side with the second semiconductor chip so that the fourth inactive surface is attached to the lower surface of the first connection member,
the second encapsulant covers at least a portion of the fourth semiconductor chip,
the second redistribution layer is also disposed on the fourth active surface of the fourth semiconductor chip, and
the second redistribution vias also electrically connect the fourth connection pads and the second redistribution layer to each other.

11. The fan-out semiconductor package of claim 1 , further comprising:
a second connection member disposed on the second encapsulant and the second redistribution layer and including a third redistribution layer electrically connected to the second redistribution layer;
a passivation layer disposed on the second connection member and having openings exposing at least a portion of the third redistribution layer;
underbump metal layers disposed in the openings of the passivation layer and connected to at least a portion of the exposed third redistribution layer; and
electrical connection structures disposed on the passivation layer and connected to the underbump metal layers.

12. The fan-out semiconductor package of claim 1 , wherein the core member includes a first insulating layer, a first wiring layer disposed on a lower surface of the first insulating layer, a second wiring layer disposed on an upper surface of the first insulating layer, and first connection vias penetrating through the first insulating layer and electrically connecting the first and second wiring layers to each other,
the first and second wiring layers are electrically connected to the first redistribution layer, and the dummy metal layer has a thickness greater than that of each of the first and second wiring layers.

13. The fan-out semiconductor package of claim 12 , wherein the core member further includes a second insulating layer disposed on the lower surface of the first insulating layer and covering the first wiring layer, a third wiring layer disposed on a lower surface of the second insulating layer, second connection vias penetrating through the second insulating layer and electrically connecting the first and third wiring layers to each other, a third insulating layer disposed on the upper surface of the first insulating layer and covering the second wiring layer, a fourth wiring layer disposed on an upper surface of the third insulating layer, and third connection vias penetrating through the third insulating layer and electrically connecting the second and fourth wiring layers to each other,
the third and fourth wiring layers are electrically connected to the first redistribution layer, and
the dummy metal layer has a thickness greater than that of each of the third and fourth wiring layers.

14. The fan-out semiconductor package of claim 1 , wherein the core member includes a first insulating layer, a first wiring layer in c

Assignees

• Samsung Electronics Co Ltd

Inventors

• Moon Seon Hee
• Kang Myung Sam
• Kim Jin Gu

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title