Integrated fan-out structure and method of forming

Patent metadata

Field	Value
Publication number	US-10068844-B2
Application number	US-201514871593-A
Country	US
Kind code	B2
Filing date	Sep 30, 2015
Priority date	Sep 30, 2015
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

A semiconductor device includes a molding compound and a through via extending through the molding compound. A via connection is disposed over the through via and a cap is disposed over the via connection. A plurality of holes are formed in a section of the cap.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a through via on a substrate, the through via extending through a molding compound;
forming a via connection disposed over and contacting the through via; and
forming a cap disposed over the through via and contacting the via connection, wherein a width of the cap is greater than a width of the through via, a line extends from a first portion of a perimeter of the cap, through a center point of the cap, to a second portion of the perimeter of the cap, the first portion being opposite to the second portion, the line extending a first distance from the center point of the cap to the first portion of the perimeter of the cap, the line extending a second distance from the center point of the cap to the second portion of the perimeter of the cap, the first distance and the second distance being the same, the center point of the cap overlying a center point of the through via, wherein a plurality of holes are formed in a first section of the cap, wherein a first hole of the plurality of holes comprises a perimeter, and a portion of the perimeter of the first hole that is closest to the via connection is laterally positioned between a perimeter of the through via and the first portion of the perimeter of the cap.

2. The method of claim 1 , wherein the first section forms a ring disposed over the perimeter of the through via in a plan view.

3. The method of claim 2 , wherein the first section extends at least 5 μm on either side of the perimeter of the through via.

4. The method of claim 1 , wherein a metal density of the cap is 50 to 70 percent of a metal density that the cap would have had without the plurality of holes.

5. The method of claim 1 , further comprising:
placing a die over the substrate;
forming a molding compound over the die;
planarizing the molding compound to expose a metal pillar of the die; and
forming one or more redistribution layers overlying the molding compound and electrically coupled to the cap and the metal pillar.

6. The method of claim 1 , wherein the via connection has a width between 10 μm to 150 μm.

7. The method of claim 1 , wherein the holes have a width of 10 μm to 50 μm.

8. The method according to claim 1 , wherein the first hole exposes a dielectric layer that extends along sidewalls of the via connection.

9. The method according to claim 1 , wherein a second hole of the plurality of holes comprises a perimeter, and the perimeter of the second hole is laterally positioned between the perimeter of the through via and a perimeter of the via connection.

10. A semiconductor device comprising:
a through via extending through a molding compound;
a via connection disposed over the through via; and
a cap disposed over the through via and contacting the via connection, wherein a width of the cap is greater than a width of the through via, and wherein a plurality of holes are formed in a first section of the cap, wherein a first hole of the plurality of holes comprises a perimeter, a first portion and a second portion of the perimeter of the first hole are laterally positioned between a perimeter of the through via and a perimeter of the via connection, the first portion being a portion of the perimeter that is closest to the via connection, the second portion being a portion of the perimeter that is farthest from the via connection.

11. The semiconductor device of claim 10 , further comprising:
a plurality of redistribution layers over the molding compound; and
a second semiconductor device bonded to the redistribution layers.

12. The semiconductor device of claim 10 , further comprising:
a die, the molding compound extending along sidewalls of the die; and
one or more redistribution layers overlying the molding compound and the die.

13. The semiconductor device of claim 10 , wherein the first section forms a ring disposed between the perimeter of the through via and the perimeter of the via connection in a plan view.

14. The semiconductor device of claim 10 , wherein the perimeter of the first hole is disposed over a dielectric layer, the via connection extending through the dielectric layer.

15. A method, comprising:
forming a through via on a substrate;
placing a die on the substrate;
encapsulating sidewalls of the through via and the die with a molding material;
forming a dielectric layer over the molding material;
forming a via connection in the dielectric layer, the via connection contacting the through via; and
forming a conductive cap over the via connection, wherein a plurality of holes are formed in the conductive cap, the holes overlying the dielectric layer, and wherein the conductive cap includes a perimeter, a first portion of the perimeter of the conductive cap is opposite to a second portion of the perimeter of the conductive cap, a first line that extends from the first portion of the perimeter of the conductive cap to the substrate extends through the molding material, a second line that extends from the second portion of the perimeter of the conductive cap to the substrate extends through the molding material, and the first line and the second line are perpendicular to a surface of the molding material, and wherein a center point of the conductive cap overlies a center point of the via connection, the center point of the conductive cap is between the first portion of the perimeter and the second portion of the perimeter, the first portion of the perimeter is a first distance from the center point of the conductive cap, the second portion is a second distance from the center point of the conductive cap, and the first distance and the second distance are the same, and wherein a hole of the plurality of holes is disposed between the first portion of the perimeter of the conductive cap and a perimeter of the via connection.

16. The method of claim 15 , wherein the holes are formed in a first section of the conductive cap, and the first section has an annular shape.

17. The method of claim 16 , wherein the first section is disposed over a perimeter of the through via.

18. The method of claim 16 , wherein the first section is disposed over the dielectric layer between a perimeter of the through via and a perimeter of the via connection.

19. The method of claim 18 , wherein the first section is offset in a plan view from the perimeter of the through via and the perimeter of the via connection.

20. The method of claim 15 , wherein the through via and the conductive cap have circular shapes in a plan view.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiu Ming-Yen
• Chen Hsien-Wei

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title