Fan-out semiconductor package

Patent metadata

Field	Value
Publication number	US-10504825-B2
Application number	US-201815988541-A
Country	US
Kind code	B2
Filing date	May 24, 2018
Priority date	Nov 3, 2017
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is connected to the stopper layer; first metal bumps disposed on the connection pads; second metal bumps disposed on an uppermost wiring layer of the wiring layers; an encapsulant covering at least portions of each of the frame, the semiconductor chip, and the first and second metal bumps and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads and the uppermost wiring layer through the first and second metal bumps.

First claim

What is claimed is:

1. A fan-out semiconductor package comprising:
a frame including
a plurality of insulating layers,
a plurality of wiring layers disposed on the plurality of insulating layers, and
a plurality of connection via layers penetrating through the plurality of insulating layers and electrically connecting the plurality of wiring layers to each other, and the frame having a recess portion having a bottom layer disposed on a bottom surface thereof;

a semiconductor chip having
connection pads,
an active surface on which the connection pads are disposed, and
an inactive surface opposing the active surface, and being disposed in the recess portion so that the inactive surface faces the bottom layer;

first metal bumps disposed on the connection pads of the semiconductor chip;
second metal bumps disposed on an uppermost wiring layer of the plurality of wiring layers;
an encapsulant covering at least portions of each of the frame, the semiconductor chip, and the first and second metal bumps and filling at least portions of the recess portion, wherein an upper surface of the encapsulant is coplanar with upper surfaces of each of the first and second metal bumps; and
a connection member including an insulating layer disposed on the coplanar upper surfaces of the encapsulant and first and second metal bumps to face the frame and the active surface of the semiconductor chip, a redistribution layer disposed on the insulating layer, and first and second connection vias penetrating through the insulating layer and integrated with the redistribution layer, the redistribution layer connected to the first and second metal bumps through the first and second connection vias, respectively.

2. The fan-out semiconductor package of claim 1 , wherein the first and second metal bumps are copper (Cu) posts.

3. The fan-out semiconductor package of claim 2 , wherein each of the first and second metal bumps has a rectangular cross-sectional shape.

4. The fan-out semiconductor package of claim 1 , wherein the plurality of insulating layers include a core insulating layer, one or more first build-up insulating layers disposed on a lower surface of the core insulating layer, and one or more second build-up insulating layers disposed on an upper surface of the core insulating layer, and
the core insulating layer has a thickness greater than that of each of the first and second build-up insulating layers.

5. The fan-out semiconductor package of claim 4 , wherein the number of first build-up insulating layers and the number of second build-up insulating layers are the same as each other.

6. The fan-out semiconductor package of claim 4 , wherein the recess portion penetrates through at least the core insulating layer and penetrates through at least one of the one or more first and second build-up insulating layers.

7. The fan-out semiconductor package of claim 1 , wherein a region of the bottom layer exposed by the recess portion has a thickness smaller than that of an edge region of the bottom layer that is not exposed.

8. The fan-out semiconductor package of claim 4 , wherein first connection vias penetrating through the first build-up insulating layer and second connection vias penetrating through the second build-up insulating layer are tapered in opposite directions to each other.

9. The fan-out semiconductor package of claim 1 , wherein walls of the recess portion are tapered.

10. The fan-out semiconductor package of claim 1 , wherein the inactive surface of the semiconductor chip is attached to the bottom layer through an adhesive member.

11. The fan-out semiconductor package of claim 1 , wherein the bottom layer is a metal layer,
at least one of the plurality of wiring layers includes a ground, and
the metal layer is electrically connected to the ground.

12. The fan-out semiconductor package of claim 1 , wherein the bottom layer has a planar area greater than that of the inactive surface of the semiconductor chip.

13. The fan-out semiconductor package of claim 1 , wherein the bottom surface of the recess portion has a planar area greater than that of the inactive surface of the semiconductor chip.

14. The fan-out semiconductor package of claim 1 , further comprising:
a first passivation layer disposed on the connection member and having openings exposing at least portions of the redistribution layer;
underbump metal layers disposed in the openings of the first passivation layer and connected to at least portions of the exposed redistribution layer; and
electrical connection structures disposed on the first passivation layer and connected to the underbump metal layers.

15. The fan-out semiconductor package of claim 14 , further comprising a second passivation layer disposed beneath the frame and having openings exposing at least portions of a lowermost wiring layer of the plurality of wiring layers.

16. The fan-out semiconductor package of claim 1 , wherein at least one of the wiring layers are disposed on a level below the bottom layer.

17. A fan-out semiconductor package, comprising:
a frame having a recess having a bottom layer disposed on a bottom surface of the recess, and having wiring layers disposed on each of an upper and a lower surface of the frame;
a semiconductor chip having an active surface and an inactive surface and being disposed in the recess such that the inactive surface contacts the bottom layer, the active surface comprising connection pads;
first metal bumps disposed on the connection pads of the semiconductor chip;
second metal bumps disposed on an uppermost wiring layer disposed on the frame;
an encapsulant covering at least portions of the frame, the semiconductor chip, the first metal bumps and the second metal bumps and filling at least a portion of the recess, wherein an upper surface of the encapsulant is coplanar with upper surfaces of each of the first and second metal bumps; and
a connection member including an insulating layer disposed on the coplanar upper surfaces of the encapsulant and first and second metal bumps to face the frame and the active surface of the semiconductor chip, a redistribution layer disposed on the insulating layer, and first and second connection vias penetrating through the insulating layer and integrated with the redistribution layer, the redistribution layer connected to the first and second metal bumps through the first and second connection vias, respectively.

18. The fan-out semiconductor package of claim 17 , wherein each of the first and second metal bumps has a rectangular cross-sectional shape.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jeong Il
• Lee Jeong Ho
• Kim Jin Su
• Cho Bong Ju

Classifications

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W72/30

  Die-attach connectors · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title