Semiconductor devices

Patent metadata

Field	Value
Publication number	US-12328866-B2
Application number	US-202318327920-A
Country	US
Kind code	B2
Filing date	Jun 2, 2023
Priority date	Sep 15, 2020
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

Semiconductor devices may include an active pattern, a gate structure in an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure on a lower portion of a sidewall of the bit line structure, and an upper spacer structure on an upper portion of the sidewall of the bit line structure. The lower spacer structure includes first and second lower spacers sequentially stacked, the first lower spacer contacts the lower portion of the sidewall of the bit line structure and does not include nitrogen, and the second lower spacer includes a material different from the first lower spacer. A portion of the upper spacer structure contacting the upper portion of the sidewall of the bit line structure includes a material different from the first lower spacer.

First claim

What is claimed is:

1. A semiconductor device comprising:
an active pattern on a substrate;
a gate structure in an upper portion of the active pattern, the gate structure extending in a first direction that is parallel to an upper surface of the substrate;
a bit line structure extending in a second direction that is parallel to the upper surface of the substrate and is perpendicular to the first direction, an upper surface of a middle portion of the active pattern in a length direction of the active pattern being recessed toward the substrate, the bit line structure contacting the upper surface of the middle portion of the active pattern, and the bit line structure including a first conductive pattern, a diffusion barrier, a second conductive pattern and a capping pattern sequentially stacked on the substrate;
a lower spacer structure extending on a portion of a sidewall of the first conductive pattern of the bit line structure, the lower spacer structure including a first lower spacer and a second lower spacer sequentially stacked on the portion of the sidewall of the first conductive pattern of the bit line structure;
an upper spacer structure extending on a portion of a sidewall of the bit line structure, the lower spacer structure not covering the portion of the sidewall of the bit line structure, and the upper spacer structure including a first upper spacer, a second upper spacer, and a third upper spacer sequentially stacked on the portion of the sidewall of the bit line structure;
a contact plug structure on one of opposing end portions of the active pattern in the length direction of the active pattern, the contact plug structure including a lower contact plug, an ohmic contact pattern, a barrier layer and an upper contact plug sequentially stacked on the substrate; and
a capacitor on the contact plug structure,
wherein the first lower spacer contacts the portion of the sidewall of the first conductive pattern of the bit line structure and does not include nitrogen, and the second lower spacer includes a material different from that of the first lower spacer,
wherein the first upper spacer contacts the portion of the sidewall of the bit line structure and includes a material different from that of the first lower spacer, and
wherein each of the first, second, and third upper spacers directly contacts an upper surface of the lower spacer structure.

2. The semiconductor device according to claim 1 , wherein the first lower spacer includes silicon oxide or silicon oxycarbide.

3. The semiconductor device according to claim 1 , wherein the first lower spacer includes oxide, and the second lower spacer includes nitride.

4. The semiconductor device according to claim 3 , further comprising third and fourth lower spacers sequentially stacked between the first and second lower spacers,
wherein the third lower spacer includes nitride, and the fourth lower spacer includes oxide.

5. The semiconductor device according to claim 1 , wherein the first lower spacer extends on a sidewall of the second lower spacer.

6. The semiconductor device according to claim 1 , wherein the first upper spacer includes nitride.

7. The semiconductor device according to claim 6 , wherein the second upper spacer is an air spacer, and
wherein the third upper spacer includes nitride.

8. The semiconductor device according to claim 1 , wherein the first upper spacer has a cross-section having an “L” shape.

9. The semiconductor device according to claim 1 , wherein upper surfaces of the second and third upper spacers are lower than an upper surface of the first upper spacer relative to the substrate.

10. The semiconductor device according to claim 1 , further comprising a fourth upper spacer extending on upper surfaces of the first, second, and third upper spacers and an outer sidewall of the third upper spacer.

11. The semiconductor device according to claim 1 , wherein the first conductive pattern includes polysilicon doped with n-type impurities, the diffusion barrier includes metal silicon nitride, the second conductive pattern includes metal, and the capping pattern includes nitride.

12. The semiconductor device according to claim 1 , wherein the lower contact plug includes doped polysilicon, the ohmic contact pattern includes metal silicide, the barrier layer includes metal nitride, and the upper contact plug includes metal.

13. The semiconductor device according to claim 1 , wherein the active pattern extends in a third direction that is parallel to the upper surface of the substrate and forms an acute angle with each of the first and second directions.

14. The semiconductor device according to claim 13 , wherein the upper surface of the middle portion of the active pattern defines a recess, and a lower portion of the bit line structure is in the recess, and
wherein the lower spacer structure extends on a sidewall of the lower portion of the bit line structure.

15. A semiconductor device comprising:
an active pattern on a substrate;
a gate structure in an upper portion of the active pattern, the gate structure extending in a first direction that is parallel to an upper surface of the substrate;
a bit line structure extending in a second direction that is parallel to the upper surface of the substrate and is perpendicular to the first direction, an upper surface of a middle portion of the active pattern in a length direction of the active pattern being recessed toward the substrate, the bit line structure contacting the upper surface of the middle portion of the active pattern, and the bit line structure including a first conductive pattern, a diffusion barrier, a second conductive pattern and a capping pattern sequentially stacked on the substrate;
a lower spacer structure extending on a portion of a sidewall of the first conductive pattern of the bit line structure, the lower spacer structure including a first lower spacer and a second lower spacer sequentially stacked on the portion of the sidewall of the first conductive pattern of the bit line structure;
an upper spacer structure extending on a portion of a sidewall of the bit line structure, the lower spacer structure not covering the portion of the sidewall of the bit line structure, and the upper spacer structure including a first upper spacer, a second upper spacer, and a third upper spacer sequentially stacked on the portion of the sidewall of the bit line structure;
a contact plug structure on one of opposing end portions of the active pattern in the length direction of the active pattern, the contact plug structure including a lower contact plug, an ohmic contact pattern, a barrier layer and an upper contact plug sequentially stacked on the substrate; and
a capacitor on the contact plug structure,
wherein the first lower spacer contacts the portion of the sidewall of the first conductive pattern of the bit line structure and does not include nitrogen, and the second lower spacer includes a material different from that of the first lower spacer,
wherein the first upper spacer contacts the portion of the sidewall of the bit line structure and includes a material different from that of the first lower spacer, and
wherein the barrier layer includes a conductive metal nitride.

16. The semiconductor device according to claim 15 , further comprising a fourth upper spacer extending on upper surfaces of the first, second, and third upper spacers and an outer sidewall of the third upper spacer.

17. The semiconductor device according to claim 16 , wherein the barrier layer is on an upper surface of the ohmic contact pattern, a side

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyosub
• Kim Keunnam
• Kim Manbok
• Kim Soojeong
• Park Chulkwon
• Jeon Seungbae
• Hwang Yoosang

Classifications

• H10B12/482 Primary

  Bit lines · CPC title

• H10B12/0335

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title

• H10B12/053

  the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383) · CPC title

• H10B12/34

  the transistor being at least partially in a trench in the substrate · CPC title

• H10B12/03

  Making the capacitor or connections thereto · CPC title