Semiconductor device with air gaps and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9786598-B2
Application number	US-201414567756-A
Country	US
Kind code	B2
Filing date	Dec 11, 2014
Priority date	Jul 25, 2014
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A semiconductor device includes: a first plug; a bit line which is in contact with the first plug and over the first plug and extended in one direction; a second plug including a first part adjacent to the bit line and a second part adjacent to the first plug; a double air gap which is disposed between the first part of the second plug and the bit line and includes a first air gap surrounding the first part of the second plug and a second air gap parallel to sidewalls of the bit line; and a capping layer suitable for capping the first and second air gaps.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first plug;
a bit line coupled to the first plug, provided over the first plug, and extending in one direction;
a first spacer over sidewalls of the bit line;
a second plug including a first part adjacent to the bit line and a second part adjacent to the first plug;
a second spacer disposed between the first spacer and the first part of the second plug, wherein the second spacer extends in parallel to the bit line;
a pillar coupled with the second spacer;
a first air gap and a second air gap which are disposed between the first part of the second plug and the bit line;
a third air gap and a fourth air gap which are disposed between the second part of the second plug and the first plug; and
a capping layer capping the first air gap and second air gap,
wherein the first air gap and the second air gap are coupled to each other,
wherein the second spacer is disposed between the first air gap and the second air gap, and
wherein the pillar is disposed between the third air gap and the fourth air gap.

2. The semiconductor device of claim 1 ,
wherein the third air gap is vertically coupled with the second air gap, and the fourth air gap is vertically coupled with the first air gap,
wherein the first air gap, the second air gap, the third air gap and the fourth air gap are coupled to each other.

3. The semiconductor device of claim 1 , wherein each of the first and the second spacers includes silicon nitride.

4. The semiconductor device of claim 1 , wherein the first air gap is directly contacted with a sidewall of the first part of the second plug.

5. A semiconductor device, comprising:
a substrate including a first region and a second region;
a first plug which is coupled to the first region;
a bit line provided over the first plug and coupled to the first plug;
a first spacer over sidewalls of the bit line;
a second plug including a first part adjacent to the bit line and a second part adjacent to the first plug, wherein the second plug is coupled with the second region;
a second spacer disposed between the first spacer and the second part of the second plug, wherein the second spacer extends in parallel to the bit line;
a first air gap and a second air gap which are disposed between the first part of the second plug and the bit line;
a third air gap and a fourth air gap which are disposed between the second part of the second plug and the first plug;
a pillar coupled with the second spacer;
a lining layer coupled with the first spacer;
a capping layer capping upper portions of the first and second air gaps;
a third plug provided over the second plug; and
a memory element provided over the third plug,
wherein the first air gap, the second air gap, the third air gap and the fourth air gap are coupled to each other,
wherein the second spacer is disposed between the first air gap and the second air gap, and
wherein the pillar is disposed between the third air gap and the fourth air gap.

6. The semiconductor device of claim 5 ,
wherein the first air gap is in a ring shape and surrounds the first part of the second plug, and
wherein the second air gap is in a line shape and extends in parallel to the bit line.

7. The semiconductor device of claim 5 , wherein the third air gap extends from the second air gap to form a continuum.

8. The semiconductor device of claim 5 ,
wherein the third air gap is vertically coupled with the second air gap, and the fourth air gap is vertically coupled with the first air gap.

9. The semiconductor device of claim 5 , wherein each of the first and the second spacers includes silicon nitride.

10. The semiconductor device of claim 5 , further comprising:
an inter-layer dielectric layer having a first opening exposing the first region of the substrate,
wherein the first plug is disposed in the first opening and spaced apart from a sidewall of the first opening by a gap.

11. The semiconductor device of claim 10 ,
wherein the lining layer covers the sidewall and a bottom surface of the gap;
wherein the pillar is spaced apart from the lining layer and extends from between the first and the second air gaps to the center of the gap,
wherein the first spacer extends in parallel to the bit line, and
wherein the second spacer extends in parallel to the first spacer.

12. The semiconductor device of claim 5 , wherein each of the lining layer, the pillar, the first spacer, and the second spacer includes silicon nitride.

13. The semiconductor device of claim 10 , further comprising:
a plug isolation layer provided over the inter-layer dielectric layer, and
a second opening passing through the plug isolation layer and the inter-layer dielectric layer and having a second opening,
wherein the second opening exposes the second region, and
wherein the second plug is disposed in the second opening.

14. The semiconductor device of claim 5 , further comprising:
a buried word line buried in the substrate and extending in a direction crossing the bit line; and
a first impurity region and a second impurity region formed in the substrate and adjacent to first and second sides of the buried word line, respectively,
wherein the first impurity region is formed in the first region, and the second impurity region is formed in the second region.

15. The semiconductor device of claim 5 , wherein the capping layer includes silicon oxide.

16. The semiconductor device of claim 5 , wherein each of the first region and the second region has a recessed surface.

17. The semiconductor device of claim 5 , wherein the first air gap is directly contacted with a sidewall of the first part of the second plug.

Assignees

• Sk Hynix Inc

Inventors

• Kim Eun-Jeong
• Lee Jin-Yul

Classifications

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W10/021

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title