Semiconductor device with air gap and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9515022-B2
Application number	US-201615170345-A
Country	US
Kind code	B2
Filing date	Jun 1, 2016
Priority date	Dec 18, 2014
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A method for fabricating a semiconductor device includes preparing a substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the substrate in the memory cell region; forming a planar gate structure over the substrate in the peripheral circuit region; forming a bit line structure over the substrate in the memory cell region; forming a first air spacers over a sidewalls of the planar gate structure; and forming a second air spacers over a sidewalls of the bit line structure.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate including a memory cell region and a peripheral circuit region;
a buried word line formed in the substrate in the memory cell region;
a bit line structure formed in the memory cell region and including a first plug and a bit line, wherein the first plug is electrically coupled to a first impurity region in the memory cell region, wherein the bit line is provided over the first plug;
a planar gate structure formed over the substrate in the peripheral circuit region;
a gate air spacer including a first air gap and positioned over a sidewall of the planar gate structure;
a second plug electrically coupled to a second impurity region in the memory cell region and including a first portion and a second portion, wherein the first portion is provided over a sidewall of the first plug, wherein the second portion extends from the first portion and is provided over a sidewall of the bit line; and
a bit line air spacer including a second air gap and positioned between the bit line structure and the second plug.

2. The semiconductor device according to claim 1 , further comprising:
a first capping layer which caps the first air gap; and
a capping strengthening layer covering the first capping layer.

3. The semiconductor device according to claim 1 , wherein the second air gap includes a line shape air gap and a plug type air gap,
wherein the line shape air gap extends in parallel to the sidewall of the bit line, and
wherein the plug type air gap extends from the line shape air gap to over the sidewall of the first plug.

4. The semiconductor device according to claim 3 , further comprising:
a second capping layer capping the line shape air gap.

5. The semiconductor device according to claim 1 , further comprising:
an ohmic contact layer over the second plug;
a third plug over the ohmic contact layer; and
a memory element over the third plug.

Assignees

• Sk Hynix Inc

Inventors

• Kwon Se-Han
• Joe Ill-Hee
• Park Dae-Sik
• Lee Hwa-Chul

Classifications

• H10W20/072 Primary

  of dielectric parts comprising air gaps · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W10/021 Primary

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title