Semiconductor package

Patent metadata

Field	Value
Publication number	US-12327784-B2
Application number	US-202217839413-A
Country	US
Kind code	B2
Filing date	Jun 13, 2022
Priority date	Sep 17, 2021
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

A semiconductor package includes an interposer substrate on a package substrate. The interposer substrate includes an upper pad on an upper surface of the insulating layer, a lower pad on a lower surface of the insulating layer, and a redistribution structure penetrating the insulating layer between the upper surface and the lower surface to connect the upper pad and the lower pad. A semiconductor chip is disposed above the interposer substrate and connected to the upper pad, and a connection bump directly contacts a lower surface of the lower pad. The redistribution structure includes redistribution layers and redistribution vias connected to the redistribution layers, wherein each of the redistribution layers and each of the redistribution vias includes a metal material layer and a plating seed layer, and the lower pad directly contacts the plating seed layer.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a package substrate;
an interposer substrate on the package substrate and including;
an insulating layer having an upper surface and an opposing lower surface,
an upper pad on the upper surface of the insulating layer,
a lower pad on the lower surface of the insulating layer, and
a redistribution structure penetrating the insulating layer between the upper surface and the lower surface to connect the upper pad and the lower pad;

a semiconductor chip disposed above the interposer substrate and connected to the upper pad; and
a connection bump directly contacting a lower surface of the lower pad,
wherein the redistribution structure includes redistribution layers and redistribution vias connected to the redistribution layers,
each of the redistribution layers and each of the redistribution vias includes a metal material layer and a plating seed layer, and
the lower pad directly contacts the plating seed layer.

2. The semiconductor package of claim 1 , wherein an upper surface of the lower pad is disposed at the same level as the lower surface of the insulating layer.

3. The semiconductor package of claim 1 , wherein the insulating layer includes at least one of SiO 2 , SiN, and SiCN.

4. The semiconductor package of claim 3 , wherein the insulating layer includes a plurality of insulating layers respectively formed of the same material.

5. The semiconductor package of claim 3 , wherein the insulating layer includes a first insulating layer formed of a first material and a second insulating layer formed of a second material different from the first material.

6. The semiconductor package of claim 3 , wherein the insulating layer includes an uppermost insulating layer, and intermediate insulating layer and a lowermost insulating layer,
each of the uppermost insulating layer and the lowermost insulating layer includes at least one of polyimide and ploybenzoxazole, and
the intermediate insulating layer includes at least one of SiO 2 , SiN and SiCN.

7. The semiconductor package of claim 1 , wherein the lower pad is formed of the same material as the metal material layer.

8. The semiconductor package of claim 7 , wherein the same material includes copper.

9. The semiconductor package of claim 1 , wherein the lower pad has an inclined side surface and a width that increases as the lower pad extends vertically upward.

10. The semiconductor package of claim 1 , wherein each redistribution via of the redistribution vias has an inclined side surface and a width that increases as the redistribution vias extend vertically upward.

11. The semiconductor package of claim 1 , wherein the redistribution vias include at least one power via, at least one ground via, and at least one signal via, and
each of the redistribution vias has a diameter that increases as each of the redistribution vias extends vertically upward.

12. The semiconductor package of claim 11 , wherein the at least one power via has a first diameter and the at least one signal via has a second diameter less than the first diameter.

13. The semiconductor package of claim 1 , wherein the redistribution vias include upper redistribution vias disposed at a first level and lower redistribution vias disposed at a second level below the first level, and
upper surfaces of the upper redistribution vias have a first diameter, and upper surfaces of the lower redistribution vias have a second diameter greater than the first diameter.

14. The semiconductor chip of claim 1 , wherein the interposer substrate has a thickness ranging from about 2.4 μm to about 10 μm.

15. The semiconductor package of claim 1 , wherein a width of the upper pad is less than a width of the lower pad.

16. The semiconductor package of claim 1 , further comprising:
an encapsulation layer covering at least a side surface of the semiconductor chip and an upper surface of the interposer substrate.

17. A semiconductor package, comprising:
an interposer substrate including an insulating layer, an upper pad on an upper surface of the insulating layer, a lower pad on a lower surface of the insulating layer, and a redistribution structure penetrating through the insulating layer to connect the upper pad and the lower pad;
a semiconductor chip disposed above the interposer substrate and connected to the upper pad; and
a connection bump directly contacting a lower surface of the lower pad,
wherein the redistribution structure includes a redistribution layer and a redistribution via connected to the redistribution layer,
the redistribution layer includes a first plating seed layer extending along a side surface and a lower surface of the redistribution layer,
the redistribution via includes a second plating seed layer extending along a side surface and a lower surface of the redistribution via, and
the lower pad directly contacts the second plating seed layer.

18. The semiconductor package of claim 17 , wherein the insulating layer includes at least one of SiO 2 , SiN, and SiCN,
the lower pad includes copper, and
at least one of the first plating seed layer and the second plating seed layer includes a material different from that of the lower pad.

19. A semiconductor package, comprising:
a package substrate;
an interposer substrate on the package substrate and including an insulating layer, an upper pad on an upper surface of the insulating layer, a lower pad on a lower surface of the insulating layer, and a redistribution structure penetrating through the insulating layer to connect the upper pad and the lower pad; and
a semiconductor chip disposed above the interposer substrate and connected to the upper pad,
wherein the insulating layer includes at least one of SiO 2 , SiN, and SiCN,
the redistribution structure includes a redistribution layer and a redistribution via connected to the redistribution layer,
the redistribution layer includes a first plating seed layer extending along a side surface and a lower surface of the redistribution layer,
the redistribution via includes a second plating seed layer extending along a side surface and a lower surface of the redistribution via, and
the lower pad directly contacts the second plating seed layer.

20. The semiconductor package of claim 19 , wherein the interposer substrate has a thickness ranging from about 2.4 μm to about 10 μm.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Sangcheon
• Kim Heonwoo
• Park Sungwoo
• Jo Chajea

Classifications

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/072

  of bump connectors · CPC title