Semiconductor package and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-10522471-B2
Application number	US-201816010872-A
Country	US
Kind code	B2
Filing date	Jun 18, 2018
Priority date	Aug 10, 2017
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

Insulating layers of a redistribution layer of a semiconductor package may be formed as a polymer film having inorganic fillers formed therein. The inorganic fillers may trap reactive materials to inhibit and/or substantially prevent the metal conductors, such as chip pads of the semiconductor chip being packaged, from being damaged by the reactive material. As a result, the reliability and the durability of the semiconductor package may be improved.

First claim

What is claimed is:

1. A semiconductor package comprising:
a semiconductor chip comprising an insulative protective layer and a plurality of conductive chip pads exposed through openings in the insulative protective layer; and
a redistribution layer including:
a plurality of insulating layers each comprising an organic film, and
a plurality of conductive redistribution patterns, each of the conductive redistribution patterns comprising a conductive interconnection portion formed on a surface of a corresponding one of the insulating layers,
wherein at least a first organic film of one of the plurality of insulating layers comprises a filler comprising a plurality of ion trapping particles formed of an inorganic material which is chemically reactive with at least one of the following ions: Cl−, K+, Na+, OH− and H+.

2. The semiconductor package of claim 1 , wherein the first organic film comprises a photosensitive polymer film having the ion trapping particles of the filler dispersed therein.

3. The semiconductor package of claim 2 , wherein at least some of the plurality of ion trapping particles of the filler are chemically combined with a corresponding chlorine ion.

4. The semiconductor package of claim 1 , wherein the inorganic material of the filler comprises at least one of a magnesium (Mg) compound and a bismuth (Bi) compound.

5. The semiconductor package of claim 1 ,
wherein the first organic film comprises a polymer film formed of a first polymer material and having the ion trapping particles of the filler dispersed therein,
wherein the ion trapping particles have a thermal conductivity higher than that of the first polymer material.

6. The semiconductor package of claim 1 ,
wherein the first organic film comprises a polymer film formed of a first polymer material and having the ion trapping particles of the filler dispersed therein,
wherein the ion trapping particles have a coefficient of thermal expansion less than that of the first polymer material.

7. The semiconductor package of claim 1 ,
wherein the plurality of conductive redistribution patterns comprise a first redistribution pattern in contact with a first chip pad of the conductive chip pads of the semiconductor chip.

8. The semiconductor package of claim 7 , wherein the first organic film is in contact with the first chip pad.

9. The semiconductor package of claim 8 , wherein the first chip pad has a surface exposed with respect to the insulative protection layer by a first hole in the insulative protection layer, and the exposed surface of the first chip pad is fully covered by the first organic film and the first redistribution pattern formed within the first hole.

10. The semiconductor package of claim 9 , wherein the first redistribution pattern comprises a conductive via and a conductive interconnection integrally formed with the conductive via, wherein the conductive via is formed within the first hole of the insulative protection layer and in contact with the first chip pad and wherein the conductive interconnection is formed on the first organic film.

11. The semiconductor package of claim 1 ,
wherein the first organic film is a first upper polymer film comprising a polymer material in which the ion trapping particles of the filler are dispersed,
wherein the plurality of insulating layers comprise a first lower polymer film directly on the first upper polymer film,
wherein the plurality of redistribution patterns comprise a first redistribution pattern in contact with a first chip pad of the conductive chip pads of the semiconductor chip and formed directly on the first lower polymer film,
wherein the first lower polymer film is a photosensitive polymer film, and
wherein the first upper polymer film has a thickness less than 70% of the thickness of the first lower polymer film.

12. A semiconductor package comprising:
a semiconductor chip comprising an insulative protective layer and a plurality of conductive chip pads exposed through openings in the insulative protective layer; and
a redistribution layer including:
a plurality of insulating layers each comprising an organic film, and
a plurality of conductive redistribution patterns, each of the conductive redistribution patterns comprising a conductive interconnection portion formed on a surface of a corresponding one of the insulating layers,
wherein at least one organic film of one of the plurality of insulating layers comprises a filler comprising a plurality of ion trapping particles formed of an inorganic material dispersed in the at least one organic film, the plurality of ion trapping particles comprised of a material that combines with a reactive material corrosive to the conductive chip pads.

13. The semiconductor package of claim 12 ,
wherein the at least one organic film comprises a polymer film formed of a first polymer material and having the ion trapping particles of the filler dispersed therein,
wherein the ion trapping particles have a thermal conductivity higher than that of the first polymer material.

14. The semiconductor package of claim 12 ,
wherein the at least one organic film comprises a first upper polymer film comprising a polymer material in which the ion trapping particles of the filler are dispersed and a first lower polymer film directly on the first upper polymer film,
wherein the plurality of redistribution patterns comprise a first redistribution pattern in contact with a first chip pad of the conductive chip pads of the semiconductor chip and formed directly on the first lower polymer film.

15. The semiconductor package of claim 14 ,
wherein the first redistribution pattern comprises a conductive via and a conductive interconnection integrally formed with the conductive via,
wherein the conductive via is formed within a hole penetrating the first upper polymer film and first lower polymer film, and the conductive via is in contact with the first chip pad, and
wherein the conductive interconnection is formed on the first lower polymer film.

16. The semiconductor package of claim 15 , wherein the conductive via has a tapered shape to have a width at the first chip pad that is smaller than a width at the conductive interconnection.

17. The semiconductor package of claim 15 , wherein the conductive via and the conductive interconnection are formed of copper.

18. A method of manufacturing comprising:
forming at least one first insulating layer on a first surface of a semiconductor chip, the first surface of the semiconductor chip comprising a plurality of metal chip pads to provide signals and power to the semiconductor chip, the plurality of metal chip pads including a first chip pad;
patterning the at least one first insulating layer to expose the metal chip pads of the semiconductor chip through corresponding openings in the at least one first insulating layer; and
forming a first redistribution pattern on the first insulating layer, the first redistribution pattern comprising a first via contacting the first chip pad and a first interconnection portion connected to the first via extending horizontally on the at least one first insulating layer,
wherein the at least one first insulating layer comprises an organic film including a plurality of ion trapping particles dispersed therein, the ion trapping particles comprising an inorganic material.

19. The method of claim 18 ,
wherein the step of forming the at least one first insulating layer on the first surface of the semiconductor chip comprises forming a first upper insulating layer on t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Suk Kyoung Lim
• Lee Seokhyun

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/9413

  on encapsulations · CPC title