Semiconductor package

Patent metadata

Field	Value
Publication number	US-11854948-B2
Application number	US-202117195774-A
Country	US
Kind code	B2
Filing date	Mar 9, 2021
Priority date	Aug 19, 2020
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

A semiconductor package includes a package substrate including a redistribution layer; a semiconductor chip disposed on the package substrate and electrically connected to the redistribution layer; a wiring structure disposed on the semiconductor chip and having an upper surface on which pads are arranged; a vertical connection structure disposed between the package substrate and the wiring structure and electrically connecting the redistribution layer and the pads; and a passivation layer disposed on the wiring structure and having openings partially exposing a region of each of the pads. The pads include a first pad adjacent to a corner of the wiring structure, and a second pad closer to a center of the wiring structure than the first pad. A first width of the first pad is greater than a second width of the second pad. A contact layer is disposed in the opening on the first pad.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first semiconductor package including:
a first package substrate including a redistribution layer,
a first semiconductor chip disposed on the first package substrate and electrically connected to the redistribution layer,
a molded member disposed on the first package substrate and covering the first package substrate and the first semiconductor chip,
a wiring structure disposed on the molded member and having an upper surface on which a plurality of upper pads are arranged, and
a frame disposed between the first package substrate and the wiring structure, having a through-hole in which the first semiconductor chip is disposed, the frame electrically connecting the redistribution layer and the plurality of upper pads;

a second semiconductor package disposed on the first semiconductor package, and including:
a second package substrate having a lower surface on which a plurality of lower redistribution pads are arranged, and
a second semiconductor chip disposed on the second package substrate and electrically connected to the plurality of lower redistribution pads; and

a plurality of connection bumps electrically connecting the plurality of upper pads and the plurality of lower redistribution pads,
wherein upper pads among the plurality of upper pads that are formed vertically under the second semiconductor package include a first upper pad adjacent to a corner of the upper surface of the wiring structure, and a second upper pad closer to a center of the upper surface of the wiring structure than the first upper pad,
the plurality of connection bumps include a first connection bump disposed in a position corresponding to the first upper pad and a second connection bump disposed in a position corresponding to the second upper pad,
a first width of the first upper pad is wider than a second width of the second upper pad,
a maximum width of the first connection bump is wider than a maximum width of the second connection bump,
a maximum thickness of the first connection bump in a vertical direction is less than a maximum thickness of the second connection bump in the vertical direction, and
the wiring structure further includes a contact layer disposed on the first upper pad between the first upper pad and the first connection bump.

2. The semiconductor package of claim 1 , wherein the first connection bump is in contact with the contact layer, and
the second connection bump is in contact with the second upper pad.

3. The semiconductor package of claim 1 , further comprising an intermetallic compound (IMC) layer between the first connection bump and the contact layer.

4. The semiconductor package of claim 1 , wherein the first width of the first upper pad is about 5% to about 10% wider than the second width of the second upper pad.

5. The semiconductor package of claim 1 , wherein the first width of the first upper pad ranges from about 250 μm to about 270 μm, and the second width of the second upper pad ranges from about 230 μm to about 250 μm.

6. The semiconductor package of claim 1 , wherein the maximum width of the first connection bump is in a range of about 220 μm to about 240 μm, and the maximum width of the second connection bump is in a range of about 200 μm to about 220 μm.

7. The semiconductor package of claim 1 , wherein a first thickness of the first connection bump in a vertical direction on the first package substrate is less than a second thickness of the second connection bump in the vertical direction.

8. The semiconductor package of claim 7 , wherein a thickness of the contact layer in the vertical direction is substantially the same as a difference between the first thickness of the first connection bump and the second thickness of the second connection bump.

9. The semiconductor package of claim 1 , wherein a thickness of the contact layer in a vertical direction on the first package substrate is in a range of about 5 μm to about 15 μm.

10. The semiconductor package of claim 1 , further comprising a passivation layer disposed on the molded member and having a plurality of openings at least partially exposing a region of each of the plurality of upper pads.

11. The semiconductor package of claim 10 , wherein the plurality of openings include a first opening at least partially exposing a region of the first upper pad, and a second opening at least partially exposing a region of the second upper pad, and
an average width of the first opening is wider than an average width of the second opening.

12. The semiconductor package of claim 11 , wherein the contact layer is disposed in the first opening, and an upper surface of the contact layer is disposed lower than an upper surface of the passivation layer.

13. The semiconductor package of claim 11 , wherein a width of a lowermost portion of the first opening is in a range of about 225 μm to about 245 μm, and a width of a lowermost portion of the second opening is in a range of about 205 μm to about 220 μm, and
a width of an uppermost portion of the first opening is in a range of about 240 μm to about 260 μm, and a width of an uppermost portion of the second opening is in a range of about 220 μm to about 240 μm.

14. The semiconductor package of claim 1 ,
wherein the frame includes:
a first insulating layer in contact with the first package substrate,
a first wiring layer in contact with the first package substrate and buried in the first insulating layer,
a second wiring layer disposed on a side opposite to a side of the first insulating layer in which the first wiring layer is buried,
a second insulating layer disposed on the first insulating layer and covering the second wiring layer, and
a third wiring layer disposed on a side opposite to a side of the second insulating layer in which the second wiring layer is buried; and

wherein the first wiring layer, the second wiring layer and the third wiring layer are electrically connected to the redistribution layer.

15. A semiconductor package comprising:
a first semiconductor package;
a second semiconductor package disposed on the first semiconductor package; and
a plurality of connection bumps electrically connecting the first semiconductor package and the second semiconductor package,
wherein the first semiconductor package includes:
a first package substrate including a redistribution layer,
a first semiconductor chip disposed on the first package substrate and electrically connected to the redistribution layer,
a wiring structure disposed on the first semiconductor chip and having an upper surface on which a plurality of upper pads are arranged, and
a vertical connection structure disposed on the first package substrate and electrically connecting the redistribution layer and the plurality of upper pads,

the second semiconductor package includes:
a second package substrate having a lower surface on which a plurality of lower redistribution pads are arranged, and
a second semiconductor chip disposed on the second semiconductor package and electrically connected to the plurality of lower redistribution pads,
each of the plurality of connection bumps are formed directly below corresponding ones of the plurality of lower redistribution pads,
upper pads among the plurality of upper pads that are formed vertically under the second semiconductor package include a first upper pad adjacent to a corner of the upper surface of the wiring structure, and a second upper pad closer to a center of the upper surface of the wiring structure than the first upper pad,
the plurality of connection bumps include a fir

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Byungho
• Shin Seongjin

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title