Semiconductor package

Patent metadata

Field	Value
Publication number	US-2023114274-A1
Application number	US-202217841155-A
Country	US
Kind code	A1
Filing date	Jun 15, 2022
Priority date	Oct 8, 2021
Publication date	Apr 13, 2023
Grant date	—

Abstract

A semiconductor package includes a redistribution structure having a first surface, an opposite second surface, and a redistribution layer between the first surface and the second surface. A semiconductor chip is on the first surface of the redistribution structure and is electrically connected to the redistribution layer. An encapsulant is on at least a portion of the semiconductor chip. A passive element is on the second surface of the redistribution structure. The passive element includes a connection surface facing the second surface, a connection terminal on the connection surface, a non-connection surface opposite to the connection surface, and a side surface extending from the connection surface to the non-connection surface. A connection bump is adjacent the passive element on the second surface and is electrically connected to the redistribution layer. A sealing material is on at least a portion of the connection surface, the non-connection surface, and the side surface of the passive element.

First claim

What is claimed is:

1 . A semiconductor package comprising:
a redistribution structure comprising a first surface, an opposite second surface, and a redistribution layer between the first surface and the second surface; a semiconductor chip on the first surface of the redistribution structure and electrically connected to the redistribution layer; an encapsulant on the semiconductor chip; a passive element on the second surface of the redistribution structure, the passive element comprising a connection surface facing the second surface of the redistribution structure, a connection terminal on the connection surface, a non-connection surface opposite to the connection surface, and a side surface extending from the connection surface to the non-connection surface; a connection bump on the second surface of the redistribution structure and electrically connected to the redistribution layer, wherein the connection bump is adjacent to the passive element; and a sealing material on each of the connection surface, the non-connection surface, and the side surface of the passive element.

2 . The semiconductor package of claim 1 , wherein the sealing material is on an entirety of each of the connection surface and the non-connection surface of the passive element.

3 . The semiconductor package of claim 1 , wherein a portion of the sealing material has a convex surface.

4 . The semiconductor package of claim 1 , wherein the sealing material has a maximum height that is lower than a maximum height of the connection bump in a direction perpendicular to the second surface.

5 . The semiconductor package of claim 1 , wherein a thickness of the sealing material on the non-connection surface of the passive element is about 1 μm or greater.

6 . The semiconductor package of claim 1 , wherein the sealing material is on an entirety of the non-connection surface of the passive element.

7 . The semiconductor package of claim 1 , wherein the sealing material comprises an insulating resin.

8 . The semiconductor package of claim 1 , wherein the passive element further comprises a connection member between the second surface of the redistribution structure and the connection surface of the passive element, wherein the connection member electrically connects the connection terminal to the redistribution layer.

9 . The semiconductor package of claim 8 , wherein the connection member comprises a portion electrically connected with the connection terminal and a solder portion electrically connecting the portion to the redistribution layer.

10 . The semiconductor package of claim 1 , wherein the passive element comprises a capacitor.

11 . The semiconductor package of claim 1 , wherein the sealing material comprises a first region on the connection surface of the passive element and on the side surface of the passive element, and a second region on the non-connection surface of the passive element, wherein the first region and the second region are spaced apart from each other.

12 . The semiconductor package of claim 1 , wherein a portion of the sealing material on the non-connection surface has a flat surface.

13 . A semiconductor package comprising:
a redistribution structure comprising a first surface, an opposite second surface, and a redistribution layer between the first surface and the second surface; a semiconductor chip on the first surface of the redistribution structure and electrically connected to the redistribution layer; a first passive element on the second surface of the redistribution structure, the first passive element comprising a first connection terminal and a first connection member electrically connecting the first connection terminal to the redistribution layer; a second passive element on the second surface of the redistribution structure, the second passive element comprising a second connection terminal and a second connection member electrically connecting the second connection terminal to the redistribution layer; and a sealing material on the first passive element, wherein the first passive element comprises a silicon (Si) capacitor and the second passive element comprises a ceramic capacitor.

14 . The semiconductor package of claim 13 , wherein the sealing material does not contact the second passive element.

15 . The semiconductor package of claim 13 , wherein
the first connection member comprises a first portion electrically connected with the first connection terminal, and a first solder portion electrically connecting the first portion to the redistribution layer, and the second connection member comprises a second solder portion electrically connecting the second connection terminal to the redistribution layer.

16 . The semiconductor package of claim 13 , wherein
the redistribution layer comprises a first pad electrically connected with the first connection member, and a second pad electrically connected with the second connection member, and the first pad has a first width in a direction that is parallel to the second surface, the second pad has a second width in the direction, and wherein the first width is less than the second width.

17 . A semiconductor package comprising:
a redistribution structure comprising a plurality of insulating layers and a plurality of redistribution layers between the plurality of insulating layers, wherein an uppermost one of the plurality of insulating layers forms a first surface of the redistribution structure, and wherein a lowermost one of the plurality of insulating layers forms an opposite second surface of the redistribution structure; a semiconductor chip on the first surface of the redistribution structure and electrically connected to the plurality of redistribution layers; a passive element on the second surface of the redistribution structure, the passive element comprising a connection surface facing the second surface of the redistribution structure, an opposite non-connection surface, and a connection terminal on the connection surface; and a sealing material on the non-connection surface of the passive element, wherein the lowermost one of the plurality of insulating layers comprises a trench therein at the second surface of the redistribution structure, and wherein the sealing material is in the trench.

18 . The semiconductor package of claim 17 , further comprising:
a connection bump on the second surface of the redistribution structure and electrically connected to the plurality of redistribution layers, wherein the connection bump and the passive element are in adjacent, spaced-apart relationship.

19 . The semiconductor package of claim 17 , wherein the trench is configured such that at least a portion of an insulating layer on the lowermost one of the plurality of insulating layers is uncovered.

20 . The semiconductor package of claim 19 , wherein the sealing material is on the at least a portion of the insulating layer that is uncovered.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jeonghyun
• Park Hwanpil
• Shim Jongbo
• Lee Eunsu
• Lee Jangwoo

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title