Stacked capacitors with shared electrodes and methods of fabrication

Patent metadata

Field	Value
Publication number	US-12324162-B1
Application number	US-202217807637-A
Country	US
Kind code	B1
Filing date	Jun 17, 2022
Priority date	Jun 17, 2022
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

A method of fabricating a system includes fabricating a plurality of transistors and coupling a forming a bridge structure connected between a gate contact of a first transistor with a drain contact of a second transistor. The method further includes fabricating a multi-level memory structure including capacitors that comprise a ferroelectric material or a paraelectric material. The capacitors within a given level are coupled together by a plate electrode. The method further includes forming a signal electrode coupled with the plate electrode.

First claim

What is claimed is:

1. A method of fabricating a device structure, the method comprising:
fabricating a plurality of transistors within a first level, wherein individual ones of the plurality of transistors comprise a source, a drain, and a gate between the source and the drain, a drain contact coupled with the drain and a gate contact coupled with the gate;
forming a bridge structure connected between the gate contact of a first transistor in the plurality of transistors to the drain contact of a second transistor in the plurality of transistors;
forming an electrode structure by forming an opening in an etch stop layer deposited above the bridge structure and by filling the opening with a conductive material, wherein the electrode structure is coupled with the bridge structure;
depositing an electrode layer on the electrode structure;
forming a first plurality of memory devices on the electrode layer by depositing a material layer stack comprising a ferroelectric material or a paraelectric material;
etching the electrode layer to form a first plate electrode;
forming a signal electrode on the first plate electrode, wherein the signal electrode is formed between a pair of memory devices of the individual ones of the first plurality of memory devices;
forming a second plate electrode above and coupled with the signal electrode; and
forming a second plurality of memory devices on the second plate electrode.

2. The method of claim 1 , wherein forming the first plate electrode comprises etching portions of the electrode layer to form the first plate electrode that extends beyond a perimeter of the individual ones of the plurality of transistors and the electrode structure.

3. The method of claim 1 , further comprising:
forming a first plurality of via electrodes, wherein individual ones of the first plurality of via electrodes are formed on the individual ones of the first plurality of memory devices; and
forming a second plurality of via electrodes, wherein individual ones of the second plurality of via electrodes are formed on individual ones of the second plurality of memory devices.

4. The method of claim 3 , further comprising forming a first plurality of conductive vias, wherein individual ones of the first plurality of conductive vias are formed on the individual ones of first plurality of via electrodes and on the signal electrode.

5. The method of claim 1 , wherein forming the signal electrode further comprises forming between an equal number of memory devices in the first plurality of memory devices on either side.

6. The method of claim 1 , wherein etching to form the first plurality of memory devices comprises partially recessing the electrode layer to form the electrode layer having a variable thickness.

7. The method of claim 4 , wherein immediately after forming the first plurality of conductive vias, the method further comprises:
depositing a second etch stop layer above the first plurality of conductive vias;
forming a second electrode structure coupled with an individual via electrode on the signal electrode, wherein forming the second electrode structure comprises forming a second opening in the second etch stop layer and by filling the opening with the conductive material;
planarizing to form the second electrode structure; and
depositing a material of the electrode layer on the second electrode structure.

8. The method of claim 7 , wherein the material layer stack is a first material layer stack, wherein the electrode layer is a first electrode layer, and wherein forming the second plate electrode and the second plurality of memory devices further comprises:
depositing a second electrode layer on the second electrode structure;
depositing a second material layer stack on the second electrode structure and patterning the second material layer stack to form the second plurality of memory devices; and
etching portions of the material of the second electrode layer to form the second plate electrode, wherein the second plate electrode extends beyond a perimeter of the individual ones of the plurality of transistors.

9. The method of claim 4 , wherein forming the first plurality of via electrodes further comprises: depositing a first dielectric above the first plurality of memory devices; forming a first via opening above the individual ones of the first plurality of memory devices; and depositing at least a first conductive hydrogen barrier material in the first via opening.

10. The method of claim 3 , wherein forming the second plurality of via electrodes further comprises: depositing a second dielectric above the second plurality of memory devices; forming a second via opening above the individual ones of the second plurality of memory devices; and depositing at least a second conductive hydrogen barrier material in the second via opening.

11. The method of claim 8 , further comprising: forming a first dielectric spacer adjacent to the individual ones of the first plurality of memory devices prior to etching the electrode layer; and forming a second dielectric spacer adjacent to the individual ones of the second plurality of memory devices prior to etching the second electrode layer.

12. The method of claim 9 , wherein forming the first plurality of conductive vias further comprises depositing a third dielectric on the first dielectric, wherein the third dielectric comprises a material that is different from the first dielectric.

13. The method of claim 8 , wherein depositing the first material layer stack and the second material layer stack comprises:
depositing the ferroelectric material comprising one of:
bismuth ferrite (BFO) or BFO with a first doping material wherein the first doping material is one of lanthanum or elements from lanthanide series of periodic table;
lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb;
a relaxor ferroelectric material which includes one of: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST);
a perovskite material which includes one of: BaTiO3, PbTiO3, KNbO3, or NaTaO3; a hexagonal ferroelectric which includes one of: YMnO3, or LuFeO3;
hexagonal ferroelectrics of a type h-RMnO3, where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y);

hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides, or their alloyed oxides; hafnium oxides as Hf (1−x) E x O y , where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y, where x and y are first and second fractions, respectively;
Al (1−x) Sc (x) N, Ga (1−x) Sc (x) N, Al (1−x) Y (x) N or Al (1−x−y) Mg (x) Nb (y) N, where x and y are third and fourth fractions, respectively;
y doped HfO 2 , where y includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y;
niobate type compounds LiNbO 3 , LiTaO 3 , lithium iron tantalum oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate; or
an improper ferroelectric material which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 and 100; or

depositing the paraelectric material comprising SrTiO 3 , Ba (x) Sr (y) TiO 3 (where x is −0.05, and y is 0.95), HfZrO 2 , Hf—Si—O, La-su

Assignees

• Kepler Computing Inc

Inventors

• Dokania Rajeev Kumar
• Sato Noriyuki
• Gosavi Tanay
• Rios Rafael
• Mathuriya Amrita
• Mukherjee Niloy
• Rathi Somilkumar J
• Manipatruni Sasikanth

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10B53/20 Primary

  characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B53/10

  characterised by the top-view layout · CPC title

• H10B12/315

  with the capacitor higher than a bit line · CPC title