Cell disturb prevention using a leaker device to reduce excess charge from an electronic device
US-2020395368-A1 · Dec 17, 2020 · US
characterised by the top-view layout
characterised by the top-view layout · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10B53/10 |
| Official title | characterised by the top-view layout |
| Display label | characterised by the top-view layout |
| Total patents | 395 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is growing.
| Year | Patents |
|---|---|
| 2015 | 7 |
| 2016 | 7 |
| 2017 | 5 |
| 2018 | 19 |
| 2019 | 10 |
| 2020 | 31 |
| 2021 | 48 |
| 2022 | 50 |
| 2023 | 64 |
| 2024 | 61 |
| 2025 | 77 |
| 2026 | 16 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Methods of incorporating leaker-devices into capacitor configurations to reduce cell disturb, and capacitor configurations incorporating leaker-devices
US-10833092-B2 · Nov 10, 2020 · US
Memory arrays
US-10825815-B2 · Nov 3, 2020 · US
Multi-level ferroelectric memory cell
US-2020295017-A1 · Sep 17, 2020 · US
Cell disturb prevention using a leaker device to reduce excess charge from an electronic device
US-10777563-B2 · Sep 15, 2020 · US
High-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor
US-2020273864-A1 · Aug 27, 2020 · US
Array Of Capacitors, Array Of Memory Cells, Methods Of Forming An Array Of Capacitors, And Methods Of Forming An Array Of Memory Cells
US-2020203357-A1 · Jun 25, 2020 · US
Memory arrays
US-2020176465-A1 · Jun 4, 2020 · US
Three-dimensional ferroelectric NOR-type memory
US-10651182-B2 · May 12, 2020 · US
Printed electronic devices exhibiting improved yield
US-10593684-B2 · Mar 17, 2020 · US
Semiconductor device having ferroelectric layer and method of manufacturing the same
US-2020066756-A1 · Feb 27, 2020 · US
Methods of Forming Memory Arrays
US-2020051849-A1 · Feb 13, 2020 · US
Semiconductor device having ferroelectric layer and method of manufacturing the same
US-10490571-B2 · Nov 26, 2019 · US
Integrated memory, integrated assemblies, and methods of forming memory arrays
US-10475697-B2 · Nov 12, 2019 · US
Apparatuses and methods including ferroelectric memory and for accessing ferroelectric memory
US-10431283-B2 · Oct 1, 2019 · US
Semiconductor devices
US-2019287965-A1 · Sep 19, 2019 · US
Frroelectric memory device and method of operating the same
US-2019259778-A1 · Aug 22, 2019 · US
Semiconductor devices
US-10347627-B2 · Jul 9, 2019 · US
Cell disturb prevention using a leaker device to reduce excess charge from an electronic device
US-2019198512-A1 · Jun 27, 2019 · US
Coated printed electronic devices exhibiting improved yield
US-10249625-B1 · Apr 2, 2019 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10B53/10?
- CPC H10B53/10 is the Cooperative Patent Classification code for “characterised by the top-view layout.”
- How many patents are filed under CPC H10B53/10 (characterised by the top-view layout)?
- Our database includes 395 publications tagged with this CPC code.
- Is patent activity under CPC H10B53/10 growing?
- Publication counts under this code: 61 in 2024 vs 77 in 2025 (latest complete years).