Transistor having dual work function buried gate electrode and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-2017069735-A1
Application number	US-201615354710-A
Country	US
Kind code	A1
Filing date	Nov 17, 2016
Priority date	Jan 29, 2014
Publication date	Mar 9, 2017
Grant date	—

Abstract

A transistor having a source region and a drain region which are separately formed in a substrate, a trench which is defined in the substrate between the source region and the drain region, and a gate electrode which is formed in the trench. The gate electrode includes a first electrode buried over a bottom of the trench; a second electrode formed over the first electrode; and a liner electrode having an interface part which is positioned between the first electrode and the second electrode and a side part, which is positioned on sidewalls of the second electrode and overlaps with the source region and the drain region.

First claim

1 - 16 . (canceled)

17 . A method for fabricating a transistor, comprising:
defining a trench in a substrate; forming a first conductive layer, which has a first work function and gapfills the trench; removing the first conductive layer from a top surface of the substrate to form a first electrode, which partially gapfills the trench; forming a second conductive layer, which has a second work function lower than the first work function, on a top surface of the first electrode, sidewalls of the trench and the top surface of the substrate; forming a barrier layer over the second conductive layer; forming a low resistance layer over the barrier layer to gapfill the trench; removing the low resistance layer, the barrier layer and the second conductive layer from the top surface of the substrate to form a second electrode and a liner electrode; and forming a source region and a drain region in the substrate, which are separated from each other by the trench and have a depth overlapping with the liner electrode.

18 . The method according to claim 17 , further comprising:
before the defining of the trench, forming an isolation layer in the substrate that defines an active region.

19 . The method according to claim 18 , further comprising:
before the forming of the first conductive layer, forming a fin region by recessing the isolation layer on a bottom of the trench.

20 . The method according to claim 17 , wherein the first conductive layer includes a material that has a work function higher than a mid-gap work function of silicon, and the second conductive layer includes a material that has a work function lower than the mid-gap work function of silicon.

21 . The method according to claim 20 , wherein the first conductive layer includes a metal nitride.

22 . The method according to claim 20 , wherein the second conductive layer includes a polysilicon, which is doped with an N-type impurity.

23 . The method according to claim 17 , wherein the barrier layer and the first conductive layer include a titanium nitride, and the low resistance layer includes tungsten.

Assignees

• Sk Hynix Inc

Inventors

• Oh Tae-Kyung
• Kim Su-Ho
• Lee Jin-Yul

Classifications

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H10D64/513 Primary

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title