Series MIM structures compatible with RRAM process

Patent metadata

Field	Value
Publication number	US-9601545-B1
Application number	US-201514883808-A
Country	US
Kind code	B1
Filing date	Oct 15, 2015
Priority date	Oct 15, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

The present disclosure relates to a method of forming an integrated circuit that prevents damage to MIM decoupling capacitors, and an associated structure. In some embodiments, the method comprises forming one or more lower metal interconnect structures within a lower ILD layer over a substrate. A plurality of MIM structures are formed over the lower metal interconnect structures, and one or more upper metal interconnect structures are formed within an upper ILD layer over the plurality of MIM structures. Together the lower and upper metal interconnect structures electrically couple the plurality of MIM structures in a series connection between a first voltage potential and a second voltage potential. By placing the MIM structures in a series connection, dissipation of the first voltage potential (e.g., a supply voltage) is spread out over the MIM structures, thereby reducing the voltage potential difference between electrodes of any one of the MIM structures.

First claim

What is claimed is:

1. A method of forming an integrated chip, comprising:
forming one or more lower metal interconnect structures within a dielectric layer over a substrate;
forming a plurality of MIM (metal-insulator-metal) structures over the one or more lower metal interconnect structures, wherein the plurality of MIM structures respectively comprise a lower electrode separated from an upper electrode by a first dielectric layer;
forming one or more upper metal interconnect structures over the plurality of MIM structures, wherein the one or more lower metal interconnect structures or the one or more upper metal interconnect structures electrically couple the plurality of MIM structures in a series connection;
forming a plurality of RRAM cells concurrent with forming the plurality of MIM structures, wherein the plurality of RRAM cells are formed in an embedded memory region laterally separated from a decoupling region comprising the plurality of MIM structures, wherein the plurality of RRAM cells respectively comprise a second lower electrode separated from a second upper electrode by a second dielectric layer; and
wherein the lower electrode is a same material as the second lower electrode, the upper electrode is a same material as the second upper electrode, and the first dielectric layer is a same material as the second dielectric layer.

2. The method of claim 1 , wherein the one or more lower metal interconnect structures comprise a metal wire layer extending in a lateral direction parallel to an upper surface of the substrate.

3. The method of claim 2 , wherein at least one of the plurality of MIM structures have an electrode in direct contact with the one or more lower metal interconnect structures.

4. The method of claim 2 , wherein the one or more lower metal interconnect structures comprise copper.

5. The method of claim 1 , wherein the lower electrode and the upper electrode comprise platinum (Pt), aluminum-copper (AlCu), titanium nitride (TiN), gold (Au), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), or copper (Cu).

6. The method of claim 1 , wherein the first dielectric layer comprises nickel oxide (NiO), titanium oxide (TiO), hafnium oxide (HfO), zirconium oxide (ZrO), zinc oxide (ZnO), tungsten oxide (WO 3 ), aluminum oxide (Al 2 O 3 ), tantalum oxide (TaO), molybdenum oxide (MoO), or copper oxide (CuO).

7. The method of claim 1 , wherein the one or more lower metal interconnect structures comprise a first lower metal interconnect structure that extends between a lower electrode of a first one of the plurality of MIM structures and a lower electrode of a second one of the plurality of MIM structures.

8. The method of claim 1 ,
wherein the plurality of MIM structures in a series connection between a first voltage potential and a second voltage potential, and
wherein the first voltage potential has a value that is greater than a dielectric breakdown voltage of the plurality of MIM structures.

9. A method of forming an integrated chip, comprising:
forming one or more lower metal interconnect structures within a lower inter-level dielectric (ILD) layer over a semiconductor substrate;
forming a plurality of MIM (metal-insulator-metal) capacitors over the one or more lower metal interconnect structures over a first region of the semiconductor substrate, wherein the plurality of MIM capacitors respectively comprise a lower electrode separated from an upper electrode by a first dielectric layer;
forming a plurality of memory cells concurrent with forming the plurality of MIM capacitors, wherein the plurality of memory cells respectively comprise a second lower electrode separated from a second upper electrode by a second dielectric layer;
forming an upper ILD layer over the plurality of MIM capacitors and the plurality of memory cells;
forming one or more upper metal interconnect structures within the upper ILD layer, wherein the one or more lower metal interconnect structures or the one or more upper metal interconnect structures are comprised within a conductive path that electrically couples the plurality of MIM capacitors in a series connection; and
wherein the lower electrode is a same material as the second lower electrode, the upper electrode is a same material as the second upper electrode, and the first dielectric layer is a same material as the second dielectric layer.

10. The method of claim 9 , wherein the plurality of MIM capacitors and the plurality of memory cells have lower surfaces that are arranged along a horizontal plane.

11. An integrated chip, comprising:
a substrate;
a lower metal interconnect layer having one or more lower metal interconnect structures arranged within a lower ILD layer over the substrate;
a plurality of MIM (metal-insulator-metal) structures arranged over the lower metal interconnect layer, and respectively comprising a first lower electrode separated from a first upper electrode by a first dielectric layer;
a plurality of memory cells arranged over the lower metal interconnect layer, and respectively comprising a second lower electrode separated from a second upper electrode by a second dielectric layer;
an upper metal interconnect layer having one or more upper metal interconnect structures arranged within an upper ILD layer over the plurality of MIM structures and the plurality of memory cells, wherein the one or more lower metal interconnect structures or the one or more upper metal interconnect structures are comprised within a conductive path that electrically couples the plurality of MIM structures in a series connection; and
wherein the first lower electrode is a same material as the second lower electrode, the first upper electrode is a same material as the second upper electrode, and the first dielectric layer is a same material as the second dielectric layer.

12. The integrated chip of claim 11 , wherein the one or more lower metal interconnect structures comprise a metal wire layer extending in a lateral direction parallel to an upper surface of the substrate.

13. The integrated chip of claim 11 , wherein at least one of the plurality of MIM structures comprises a lower electrode in direct contact with the one or more lower metal interconnect structures.

14. The integrated chip of claim 11 , wherein at least one of the plurality of MIM structures comprises:
an upper electrode; and
a metal connection layer arranged between the upper electrode and the one or more upper metal interconnect structures, wherein the metal connection layer comprises a same material as the one or more upper metal interconnect structures.

15. The integrated chip of claim 12 , further comprising:
one or more dielectric layers vertically arranged between the metal wire layer and the substrate, wherein the one or more dielectric layers comprise additional metal wire layers.

16. The integrated chip of claim 11 ,
wherein the plurality of memory cells are aligned with the plurality of MIM structures and arranged in an embedded memory region laterally separated from a decoupling region comprising the plurality of MIM structures.

17. The integrated chip of claim 11 , wherein the lower ILD layer is vertically separated from the substrate by one or more additional inter-level dielectric layers.

18. The integrated chip of claim 11 , wherein the lower metal interconnect layer comprises copper.

19. The integrated chip of claim 11 , wherein the lower metal interconnect layer is vertically separated from the substrate by one or more additional inter-

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tu Kuo-Chi
• Yang Chin-Chieh
• Chu Wen-Ting

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H01L45/16

  Electricity · mapped topic