Memory device, and manufacturing method and driving method thereof

Patent metadata

Field	Value
Publication number	US-12317503-B2
Application number	US-202217661369-A
Country	US
Kind code	B2
Filing date	Apr 29, 2022
Priority date	Jan 18, 2022
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

The present disclosure relates to the technical field of semiconductor manufacturing, and in particular, to a memory device, and a manufacturing method and a driving method thereof. The memory device includes: a substrate; a stacked structure, where the stacked structure includes a first gate layer, a second gate layer, and interlayer isolation layers, one of the interlayer isolation layers is located between the first gate layer and the second gate layer, and another one of the interlayer isolation layers is located between the first gate layer and the substrate; and a memory structure, including a through hole penetrating the stacked structure, and a trench structure filled in the through hole. The present disclosure enables the memory device to be used as nonvolatile memory with different storage modes, thereby realizing versatility of the memory device.

First claim

The invention claimed is:

1. A memory device, comprising:
a substrate;
a stacked structure, wherein the stacked structure comprises a first gate layer, a second gate layer, and interlayer isolation layers, one of the interlayer isolation layers is located between the first gate layer and the second gate layer, and another one of the interlayer isolation layers is located between the first gate layer and the substrate; and
a memory structure, comprising a through hole penetrating through the stacked structure, and a trench structure filled in the through hole;
wherein the trench structure comprises a tunneling layer covering an inner wall of the through hole, a charge capture layer covering a surface of the tunneling layer, a ferroelectric layer covering a surface of the charge capture layer, an insulating buffer layer covering a surface of the ferroelectric layer, and a channel layer covering a surface of the insulating buffer layer;
the channel layer penetrates through the tunneling layer, the charge capture layer, the ferroelectric layer, and the insulating buffer layer, which are at a bottom of the through hole; and a bottom surface of the channel layer comes into contact with the substrate; and
the memory device further comprises:
a drain, wherein the drain is connected to a top surface of the channel layer in a contact manner;
wherein the trench structure further covers a top surface of the stacked structure, and the drain penetrates through the trench structure located on the top surface of the stacked structure.

2. The memory device according to claim 1 , wherein there are a plurality of memory structures, and the plurality of memory structures are arranged in an array along a first direction and a second direction.

3. The memory device according to claim 2 , wherein the first gate layer comprises a plurality of first gate structures that are parallel spaced along the second direction, the second gate layer comprises a plurality of second gate structures that are parallel spaced along the second direction, the plurality of second gate structures are located above the plurality of first gate structures; and a plurality of memory structures, that are arranged in parallel along the first direction, share the plurality of first gate structures and the plurality of second gate structures.

4. The memory device according to claim 3 , further comprising:
a separation structure, wherein the separation structure penetrates through the stacked structure along a direction perpendicular to a top surface of the substrate, and the separation structure is located between two adjacent ones of the plurality of first gate structures and between two adjacent ones of the plurality of second gate structures.

5. The memory device according to claim 3 , wherein a material of the plurality of first gate structures is a metallic material, and a material of the plurality of second gate structures is a polycrystalline silicon material.

6. A driving method of the memory device according to claim 1 , comprising:
in a first storage mode, applying a first turn-on voltage to the second gate layer and applying a first storage voltage to the first gate layer, to write information into a ferroelectric layer; and
in a second storage mode, applying a second turn-on voltage to the second gate layer and applying a second storage voltage to the first gate layer, to write information into a charge capture layer.

7. The driving method of the memory device according to claim 6 , further comprising:
in the first storage mode, applying a first reading voltage to the first gate layer to read information stored in the ferroelectric layer; and
in the second storage mode, applying a second reading voltage to the first gate layer to read information in the charge capture layer.

8. The driving method of the memory device according to claim 6 , further comprising:
in the first storage mode, applying a first erasing voltage to the first gate layer to erase the information stored in the ferroelectric layer; and
in the second storage mode, applying a second erasing voltage to the first gate layer to erase the information stored in the charge capture layer.

9. A manufacturing method of a memory device, comprising:
providing a substrate;
forming a stacked layer, wherein the stacked layer comprises a first interlayer isolation layer, a sacrificial layer, a second interlayer isolation layer, and a second gate layer that are successively stacked on the substrate;
etching the stacked layer to form a through hole penetrating through the stacked layer;
forming a trench structure in the through hole; and
removing the sacrificial layer and replacing the sacrificial layer with a conductive material to form a first gate layer;
wherein the forming a trench structure in the through hole comprises:
forming a tunneling layer on an inner wall of the through hole and on a top surface of the stacked layer;
forming a charge capture layer on a surface of the tunneling layer;
forming a ferroelectric layer on a surface of the charge capture layer;
forming an insulating buffer layer on a surface of the ferroelectric layer;
etching the insulating buffer layer, the ferroelectric layer, the charge capture layer, and the tunneling layer, which are at a bottom of the through hole, to form a penetrating hole exposing the substrate; and
forming a channel layer that fills up the penetrating hole and covers a surface of the insulating buffer layer;
wherein the manufacturing method further comprises:
etching at least a part of the trench structure on the top surface of the stacked layer to form a drain hole exposing the channel layer in the through hole; and
filling the drain hole to form a drain.

10. The manufacturing method of a memory device according to claim 9 , wherein the forming a through hole penetrating through the stacked layer specifically comprises:
etching the stacked layer to form a plurality of through holes penetrating through the stacked layer, wherein the plurality of through holes are arranged in an array along a first direction and a second direction, the first direction and the second direction are parallel to a top surface of the substrate, and the first direction intersects with the second direction.

11. The manufacturing method of a memory device according to claim 9 , wherein the forming a first gate layer specifically comprises:
etching the stacked layer to form a plurality of separation slots that are arranged in parallel along a second direction and penetrate to a top surface of the first interlayer isolation layer; wherein each of the plurality of separation slots is located between two adjacent through holes arranged in parallel along the second direction, to divide the second gate layer into a plurality of second gate structures arranged in parallel along the second direction;
removing the sacrificial layer along the separation slots to form a gap region; and
filling the conductive material in the gap region along the separation slots to form the first gate layer.

12. The manufacturing method of a memory device according to claim 11 , further comprising:
removing the conductive material in the separation slots; and
filling an insulating material in the separation slots to form a separation structure, wherein the separation structure separates the first gate layer into a plurality of first gate structures arranged in parallel along the second direction.

13. The manufacturing method of a memory device according to claim 9 , wherein a material of the first gate layer is a metallic material, and a material of the second gate layer is a polycrystalline silicon mat

Assignees

• Changxin Memory Tech Inc

Inventors

• Guo Shuai
• Zuo Mingguang
• Bai Shijie

Classifications

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D64/689

  having ferroelectric layers · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D64/033

  comprising ferroelectric layers · CPC title