Nonvolatile memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10079247-B2
Application number	US-201715632146-A
Country	US
Kind code	B2
Filing date	Jun 23, 2017
Priority date	Nov 9, 2016
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

Disclosed is a method of manufacturing a nonvolatile memory device. In the method, a stacked structure is formed on a conductive substrate structure. The stacked structure includes at least one interlayer insulating layer and at least one sacrificial layer alternately stacked with the at least one interlayer insulating layer. A first trench is formed to extend through the stacked structure and to expose the conductive substrate structure. A first gate electrode layer, a dielectric structure, and a channel layer are formed on a side wall of the first trench, the dielectric structure including a ferroelectric layer. At least one recess is formed to expose a side wall of the first gate electrode layer by removing the at least one sacrificial layer. At least one second gate electrode layer is formed by filling the at least one recess with a conductive layer.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a conductive substrate structure;
a stacked structure disposed on the conductive substrate structure, the stacked structure including at least one interlayer insulating layer and at least one horizontal gate electrode layer alternately stacked with the at least one interlayer insulating layer;
a first trench extending through the stacked structure and into the conductive substrate structure;
a vertical gate electrode layer disposed directly on a side wall of the first trench and contacting the at least one interlayer insulating layer and the at least one horizontal gate electrode layer;
a ferroelectric structure disposed on the vertical gate electrode layer; and
a channel layer disposed on the ferroelectric structure.

2. The nonvolatile memory device of claim 1 , further comprising:
a second trench extending through the stacked structure and into the conductive substrate structure;
a source line connection pattern disposed in the second trench, the source line connection pattern being electrically insulated from the vertical gate electrode layer, and being connected to the conductive substrate structure and to a source line; and
a bit line connection pattern disposed over the first trench and connected to the channel layer and a bit line.

3. The nonvolatile memory device of claim 1 , wherein the at least one horizontal gate electrode layer comprises at least one of a metal, a metal nitride material, a metal carbide material, and a metal silicide.

4. The nonvolatile memory device of claim 1 , wherein the vertical gate electrode layer comprises a doped silicon layer covering the side wall of the first trench.

5. The nonvolatile memory device of claim 1 , wherein the ferroelectric structure comprises at least one selected from the group consisting of hafnium oxide, hafnium silicon oxide, zirconium oxide, and zirconium silicon oxide.

6. The nonvolatile memory device of claim 1 , wherein the channel layer comprises a doped silicon layer.

7. The nonvolatile memory device of claim 1 , wherein the at least one horizontal gate electrode is connected to a plurality of different word lines, respectively, and
wherein a polarization state of a portion of the ferroelectric structure adjacent to the at least one horizontal gate electrode layer is independently controlled according to a voltage applied through each of the different word lines.

8. The nonvolatile memory device of claim 3 , wherein the at least one horizontal gate electrode layer comprises at least one selected from the group consisting of a tungsten (W), titanium (Ti), copper (Cu), a tungsten nitride material, a titanium nitride material, a tantalum nitride material, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

9. The nonvolatile memory device of claim 5 , wherein the ferroelectric structure includes a dopant comprising at least one selected from the group consisting of copper (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), and gadolinium (Gd).

Assignees

• Sk Hynix Inc

Inventors

• Kim Joong Sik

Classifications

• H01L27/11597 Primary

  Electricity · mapped topic

• H01L29/42356

  Electricity · mapped topic

• H01L29/4966

  Electricity · mapped topic

• H01L29/495

  Electricity · mapped topic

• H10D30/792

  comprising applied insulating layers, e.g. stress liners · CPC title